Rename SOC_STM32L476XX to SOC_STM32L476XG to keep flash
size information.
Aim is to be able to distinguish flash size variants of
the SoC when needed (for instance in dts/arm/st/mem.h file)
Change-Id: I834bb5b83c24c39e90c0492a2b22a7c7802de361
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
The xC tag in the SoC reference indicates the flash size, use it in the
configuration to permit selection of correct flash size for dts.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reorder config entries alphabetically to make it easier to add new ones.
Change-Id: Ib118405a150a408638232513fba7198b458ecfa7
Signed-off-by: Florian Vaussard <florian.vaussard@heig-vd.ch>
Add support for STM32L475xG SoC as a preliminary for
Discovery IOT board support.
stm32l476.dtsi file is now including stm32l475.dtsi
since STM32L476 SoC is a STM32L475 SoC with LCD support
Change-Id: I7567255e4172231cbf4899474617ecae0cd68d64
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Following activation of stm32 common clock driver for stm32f4 series
remove references to stm32f4 specific driver.
Change-Id: I372a0ea046007bcb34944d6b2b8880077583b1d3
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This commit disables native stm32f4x clock control
driver and enables stm32 LL clock control driver
for stm32f4 family
Jira: ZEP-2039
Change-Id: I98ba6c89c4a3a1f39658c5808cd47a2d1f344130
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This commit enables STM32Cube LL based driver for stm32f4 series.
This generic driver provides a unified API to clock driver for all
stm32 series.
LL API allows driver to be lightweight and to keep genericity across
stm32 family to ease further devlopment and maintenance.
Change-Id: Ie31ae8f433313787f9c9eda77de41925721d54dd
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This patch adds initial MPU support to STM32F401XE.
The boot configuration prevents the following security issues:
* Prevent to read at an address that is reserved in the memory map.
* Prevent to write into the boot Flash/ROM.
* Prevent the application to access to the BootROM.
* Prevent from running code located in SRAM.
Change-Id: I4dc0669009bd5c0a829a69f8ff417c787b7043ed
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@linaro.org>
Document the flash latency values by copying the relevant tables
from the reference manuals for each MCU.
Change-Id: Ieb2824ffd7634d917399e3e62146d9243b527f44
Signed-off-by: Christer Weinigel <christer@weinigel.se>
If the flash latency isn't set most STM32F4xx MCU's won't be able
to run from flash when the CPU frequency is changed. Make this a
compile time error instead of an assert at runtime.
Change-Id: Ic3421194545f8f83bd6e00f0cd011306c8d1eedd
Signed-off-by: Christer Weinigel <christer@weinigel.se>
Convert code to use u{8,16,32,64}_t and s{8,16,32,64}_t instead of C99
integer types. There are few places we dont convert over to the new
types because of compatiability with ext/HALs or for ease of transition
at this point. Fixup a few of the PRI formatters so we build with newlib.
Jira: ZEP-2051
Change-Id: I7d2d3697cad04f20aaa8f6e77228f502cd9c8286
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This is a start to move away from the C99 {u}int{8,16,32,64}_t types to
Zephyr defined u{8,16,32,64}_t and s{8,16,32,64}_t. This allows Zephyr
to define the sized types in a consistent manor across all the
architectures we support and not conflict with what various compilers
and libc might do with regards to the C99 types.
We introduce <zephyr/types.h> as part of this and have it include
<stdint.h> for now until we transition all the code away from the C99
types.
We go with u{8,16,32,64}_t and s{8,16,32,64}_t as there are some
existing variables defined u8 & u16 as well as to be consistent with
Zephyr naming conventions.
Jira: ZEP-2051
Change-Id: I451fed0623b029d65866622e478225dfab2c0ca8
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Since all STM32 SoCs are using device tree we can remove this last bit
of !HAS_DTS for getting flash/sram sizes from Kconfig.
Change-Id: I9e706b7aba7c0edcf9fca3ddc0ddc7d820980b47
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Converted over all STM32F3 based boards to use device tree and removed
associated bits that now come from the device tree for STM32F3.
Boards that are now using devicetree:
* Nucleo f334r8
* STM32373C Eval
Change-Id: I081a1d83f86e417a98b6864c745354b6b32953b7
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Converted over all STM32F1 based boards to use device tree and removed
associated bits that now come from the device tree for STM32F1. Also
renamed the STM32F10{3,7} SoC dtsi to try and make it clear that the 'X'
is a place holder. Fixedup the top level compatiables in the boards to
be the specific 'X' instead of the generic one.
Boards that are now using devicetree:
* Nucleo f103rb
* STM3210C Eval
* STM32 MINI A15
Change-Id: I29b3634ec7451f974687d55980414efa655e2e96
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Converted over all STM32F4 based boards to use device tree and removed
associated bits that now come from the device tree for STM32F4.
Boards that are now using devicetree:
* 96b_carbon
* nucleo f401re
* nucleo f411re
Change-Id: Ibe197ca0a3f5ad78d594485a578d986403cc824a
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Since all the L4 SoCs are using DTS we can remove the various Kconfig
bits that we now get from DTS.
Change-Id: Icdec49b478ff285dc3347b09412964a721f75bbf
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Move back to getting the number of IRQs from Kconfig. We do this
because the number of IRQs should really just be determined by scanning
the device tree and figuring out the highest IRQ value used.
Change-Id: I8e0dbec1d9d036d4e899b237c4dc7d833c422e18
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
The Cortex-M4 of the STM32F4 family has an FPU. Enable the FPU support
by selecting CPU_HAS_FPU.
Change-Id: Iddae9c547df6e010562649eb0997dc61563c8fc4
Signed-off-by: Florian Vaussard <florian.vaussard@heig-vd.ch>
The comment refers to STM32F1 instead of STM32F4.
Change-Id: Ide116b712146f87a6f4d2aaafea8bd181c4d9397
Signed-off-by: Florian Vaussard <florian.vaussard@heig-vd.ch>
The current implementation of stm32_gpio_set() uses the GPIO output data
register to change the state of individual GPIOs. The generated
assembler needs at least 3 instructions: load / modify / store.
This opens a small race window, for example if a thread and an
interrupt both try to change the state of the same GPIO bank.
Use the GPIO bit set/reset register to perform the atomic change without
locking.
This also has the benefit of a more optimised implementation, which can
be useful for GPIO-intensive work. Compare the new version:
08000c98 <stm32_gpio_set>:
8000c98: f001 010f and.w r1, r1, #15
8000c9c: 2301 movs r3, #1
8000c9e: b902 cbnz r2, 8000ca2 <stm32_gpio_set+0xa>
8000ca0: 3110 adds r1, #16
8000ca2: 408b lsls r3, r1
8000ca4: 6183 str r3, [r0, #24]
8000ca6: 2000 movs r0, #0
8000ca8: 4770 bx lr
and the old one:
08000c98 <stm32_gpio_set>:
8000c98: 2301 movs r3, #1
8000c9a: f001 010f and.w r1, r1, #15
8000c9e: fa03 f101 lsl.w r1, r3, r1
8000ca2: 6943 ldr r3, [r0, #20]
8000ca4: b10a cbz r2, 8000caa <stm32_gpio_set+0x12>
8000ca6: 4319 orrs r1, r3
8000ca8: e001 b.n 8000cae <stm32_gpio_set+0x16>
8000caa: ea23 0101 bic.w r1, r3, r1
8000cae: 6141 str r1, [r0, #20]
8000cb0: 2000 movs r0, #0
8000cb2: 4770 bx lr
Change-Id: Ie5800d1c345016028d1b9a099f5d74cac35f592a
Signed-off-by: Florian Vaussard <florian.vaussard@heig-vd.ch>
This patch adds the necessary changes to enable use of DTS for
generating required build information.
Change-Id: I0d7aa15488339a425ffe57b6354992851212f7f3
Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
The previous file contained erroneous values of the number of IRQs
in these socs.
Change-Id: Ie7d2c19d86e247599f4924b95d9330175140d894
Signed-off-by: Gustavo Denardin <gustavo.denardin@gmail.com>
Cube HAL implements timeout based on 1ms tick.
This commit allows Cube HAL to get Zephyr system clock.
Change-Id: I9a59edcf6fa8e0ebfd5040348db537dadd9fcdfa
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
In order to support the discovery STM32F4 and STM32F429 boards,
it is necessary to make these socs available.
Change-Id: I351d294fb02c4385f291a6e258a3f7d81e85627e
Signed-off-by: Gustavo Denardin <gustavo.denardin@gmail.com>
Pin number should be decremented by 8 if the pin
refers to the GPIOx_AFRH register.
Change-Id: I76e960f3b4adc3c2139ef5a88f15dbe98603228e
Signed-off-by: Adam Podogrocki <adam.podogrocki@rndity.com>
Following activation of Cube LL based clock control driver,
this commits cleans up the useless structures for RCC definitions
and remove code relative to native F3 Clock control driver.
Change-Id: I6f3ee44adb09adc52927eb4b05f8a829665eb96d
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Following activation of Cube LL based clock control driver,
this commits cleans up the useless structures for RCC definitions
and remove code relative to native L4 Clock control driver.
Change-Id: Ic0408d5f5ec66651d46d13dfaf447da2666367cd
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
After introduction of STM32Cube based clock control driver for
stm32 family, provide its support on stm32f3x soc.
Clean up will have to be done afterwards.
Change-Id: I20480579f12a6fc1f1f6a51589981ac3f1d63ef0
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
After introduction of STM32Cube based clock control driver for
stm32 family, provide its support on stm32l4x soc.
Clean up will have to be done afterwards.
Change-Id: I979a4169148c5fe5a0693d182d2d17f9ffaf1c77
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This patch adds all the necessary changes to enable use of DTS for
generating required build information.
Change-Id: Ia476fbb14c7d9d6b9db3340c73f599556a880da3
Signed-off-by: Andy Gross <andy.gross@linaro.org>
A number of SoCs clear out the Mem/Bus/Usage and Hard Fault exceptions
during init. Lets refactor that into a common function so we don't have
to keep duplicating it over and over.
Change-Id: Ida908a9092db37447abcf3c9872f36937982f729
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
The STM32 GPIO driver extended the generic GPIO driver interace with
the concept of OPEN_DRAIN. There is previous discussion about
representing such concepts in the GPIO interface in a more general
fashion here:
https://lists.zephyrproject.org/archives/list/devel@lists.zephyrproject.org/thread/6DCFUAKCOOOBHUO3ZK45ES6IQXOEOFWN/
The DRIVE STRENGTH interface supports the concepts of OPEN DRAIN and
other variants supports by other vendors hardware.
Adjust the STM32 GPIO driver to use the DRIVE STRENGTH interface. A
following patch will address the simplication of gpio.h
Change-Id: I56b0792ec2b21f1adc673dff019288dc8573d005
Signed-off-by: Marcus Shawcroft <marcus.shawcroft@arm.com>
Implementation includes adding some defines in the pinmux,
adjusting gpio driver to specific defines for STM32F3X family,
adding specific functionality in the F3X SoC definition.
Change-Id: I465c66eb93e7afb43166c4585c852e284b0d6e67
Signed-off-by: Adam Podogrocki <adam.podogrocki@rndity.com>
It is called before early SoC initialization, so remove the duplicated
code from other boards and just set it by default when using XIP.
This can later be used when adding bootloader support, as an
additional option could be created to move the VTOR offset to a
different address.
Change-Id: Ia1f5d9a066de61858ee287215cefdd58596b6b1c
Signed-off-by: Ricardo Salveti <ricardo.salveti@linaro.org>
Replace the existing Apache 2.0 boilerplate header with an SPDX tag
throughout the zephyr code tree. This patch was generated via a
script run over the master branch.
Also updated doc/porting/application.rst that had a dependency on
line numbers in a literal include.
Manually updated subsys/logging/sys_log.c that had a malformed
header in the original file. Also cleanup several cases that already
had a SPDX tag and we either got a duplicate or missed updating.
Jira: ZEP-1457
Change-Id: I6131a1d4ee0e58f5b938300c2d2fc77d2e69572c
Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This patch provides initial support for the SoC STM32F107. This SoC
belongs to the Connectivity Line devices.
Connectivity line family incorporates up to 14 communication
interfaces such as: 2 x I2C, 5 x USART, 3 x SPI, 2 x CAN, USB 2.0,
10/100 Ethernet MAC.
Change-Id: I5cb2c458bce9ec1558b4168e87a7003ad9f606a5
Signed-off-by: Adam Podogrocki <adam.podogrocki@rndity.com>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
stm32f411re SoC could run at system clock above 84MHz.
This was not taken into account in __setup_flash function which configure
flash latency depending on system clock. This is now corrected.
Assert added to ease error detection.
Change-Id: I49b92256d611ef464171fb1d8812a4c4d3c27ab8
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
replace include <nanokernel.h> with <kernel.h> everywhere and also fix
any remaining mentions of nanokernel.
Keep the legacy samples/tests as is.
Change-Id: Iac48447bd191e83f21a719c69dc26233216d08dc
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Erwan Gouriou