Commit Graph

16 Commits

Author SHA1 Message Date
Andrew Boie 2d9bbdf5f3 x86: remove support for non-PAE page tables
PAE tables introduce the NX bit which is very desirable
from a security perspetive, back in 1995.

PAE tables are larger, but we are not targeting x86 memory
protection for RAM constrained devices.

Remove the old style 32-bit tables to make the x86 port
easier to maintain.

Renamed some verbosely named data structures, and fixed
incorrect number of entries for the page directory
pointer table.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2019-02-05 20:51:21 -08:00
Anas Nashif d9ec5eca24 hpet: remove HPET_TIMER_*_EDGE and HPET_TIMER_LEVEL_*
This option is not used anywhere and was removed when the hpet driver
was rewritten.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2019-01-22 07:45:22 -05:00
Anas Nashif 1d11945739 hpet: remove unused HPET_TIMER_LEGACY_EMULATION
This option is not used anywhere and was removed when the hpet
driver was rewritten.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2019-01-22 07:45:22 -05:00
Andrew Boie 1c5642a402 boards: x86: don't turn on mem protection
This is not enabled at the board level.
tests/Kconfig turns this on for test cases.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2018-11-28 15:33:11 -08:00
Andy Ross 225c74bbdf kernel/Kconfig: Reorgnize wait_q and sched algorithm choices
Make these "choice" items instead of a single boolean that implies the
element unset.

Also renames WAITQ_FAST to WAITQ_SCALABLE, as the rbtree is really
only "fast" for large queue sizes (it's constant factor overhead is
bigger than a list's!)

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2018-07-03 17:09:15 -04:00
Andy Ross f8288abd22 boards/qemu_x86: Enable fast scheduler options
This target is already using the rbtree as part of CONFIG_USERSPACE,
so it incurs no code size overhead (actually it's a little smaller)
when using the scalable scheduler and waitq implementations.

The change also gets us test coverage of those choices on a default CI
target.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2018-05-19 07:00:55 +03:00
Andrew Boie 1c5e6b2d3e qemu_x86: enable CONFIG_DEBUG_INFO
Minimal performance cost and will enable runtime stack traces.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2018-03-16 14:12:15 -07:00
Adithya Baglody f677caef2d x86: MMU: Set PAE page tables for QEMU as default.
Replacing the default paging scheme from 32-bit paging to
PAE paging in QEMU.

JIRA:ZEP-2511

Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
2017-10-25 10:39:47 -07:00
Andrew Boie 911be99edf Revert "x86: MMU: Set PAE page tables..."
This reverts commit
0b6bc24089.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-10-24 12:45:59 -07:00
Adithya Baglody 0b6bc24089 x86: MMU: Set PAE page tables for QEMU as default.
Replacing the default paging scheme from 32-bit paging to
PAE paging in QEMU.

JIRA:ZEP-2511

Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
2017-10-23 10:13:07 -07:00
Andrew Boie ec896b9796 qemu_x86: enable userspace and app memory
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-10-13 12:56:14 -07:00
Andrew Boie 17876c857a qemu_x86: enable HW stack protection properly
CONFIG_X86_STACK_PROTECTION is now a hidden option enabled by
CONFIG_HW_STACK_PROTECTION.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-09-11 12:26:54 -07:00
Andrew Boie 19fdf4d6f8 qemu_x86: enable MMU stack protection by default
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-07-25 11:32:36 -04:00
Andrew Boie dbd705228b qemu: enable MMU by default
We have lots of RAM, this helps catch bugs.
Enable XIP as well, this used to be turned on but was
shut off for some reason.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-07-10 11:44:56 -07:00
Anas Nashif 7318fa22a2 boards: qemu: enable test random generator
This should be a default option for this board which would allow us to
remove it from many sample configurations that can be then used for
other boards.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-07-05 12:43:13 -04:00
Kumar Gala 8d35760fec board: organize boards based on architecture
Introduce an architecture sorting of boards.  This is to allow for
easier maintenance going forward as the number of boards grows.  It
will be easier for any scripts to know the board/arch mapping without
having to maintain an explicit list of what boards are associated with
which arch.  We can also do things like have architecture maintainers
cover reviews and branches for arch/${ARCH} and boards/${ARCH} going
forward.

Change-Id: I02e0a30292b31fad58fb5dfab2682ad1c5a7d5a7
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2016-10-24 19:59:42 +00:00