Fixes a bug in _ExcEntSetupDone wherein the return address to the
exception stub was accidentally changed to point to the TCS of the
interrupted thread.
Jira: ZEP-378
Change-Id: I0e502649c49c35ba8b2457016ede4a6b586da3fb
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
Fibers initialize this back pointer to NULL as they are (by definition)
not microkernel tasks. Microkernel tasks initialize it to their
corresponding 'ktask_t'.
However for nanokernel systems, the back pointer is always NULL. This
is because there is only one task in a nanokernel system (the background
task) and it can not pend on a nanokernel object--it must poll.
Change-Id: I9840fecc44224bef63d09d587d703720cf33ad57
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
We really should have more faith in the compiler, it generates
code to implement this exactly like the arch-specific assembly
versions, and on ARM is actually 4 bytes shorter.
FUNC_NO_FP used to disable the usual C preamble to update the
frame/stack pointers, which is how the sizes are still the same
or less. It's debatable how useful the occasional use of
FUNC_NO_FP is in practice since it hinders debugging and in a
production build frame pointers should be globally disabled, but
we can address that later.
Change-Id: I6c4b64ab3e3a9b6f91d52fa8c92e6e79a986fc77
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Of the 3 related functions;
_thread_essential_set()
_thread_essential_clear()
_is_thread_essential()
The first two are parameter-less and always operate on
"_nanokernel.current". The last one takes a 'thread' parameter but will
operate on _nanokernel.current if the parameter is NULL. All calls to
_is_thread_essential() pass NULL!
This change makes the 3 functions consistent by removing the parameter
to the 3rd function. This should also be marginally more efficient,
though consistency was the motivation. This change corrects the doc
preamble to all 3 functions.
(These functions would probably be better as inlines. Also, the choice
of when to use wrappers seems a bit arbitrary. E.g. there's nothing
for setting/testing the "FIBER" flag.)
Change-Id: Ie3589f8a28b227c6d7a3a31b664d3b3e6e9c6d17
Signed-off-by: Geoff Thorpe <geoff.thorpe@nxp.com>
GDB server needs ownership of some exceptions to display information when
taking a fatal exception (DIVIDE_ERROR, PAGE_FAULT).
Introduce a Kconfig option that can work for any debugger.
Change-Id: I39aef22a820543a7fe9ac333b487592946abc0f3
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
The GDB server implements a set of GDB commands, such as read/write
memory, read/write registers, connect/detach, breakpoints, single-step,
continue. It is not OS-aware, and thus provides a 'system-level'
debugging environment, where the system stops when debugging (such as
handling a breakpoint or single-stepping).
It currently only works over a serial line, taking over the
uart_console. If target code prints over the console, the GDB server
intecepts them and does not send the characters directly over the serial
line, but rather wraps them in a packet handled by the GDB client.
Change-Id: Ic4b82e81b5a575831c01af7b476767234fbf74f7
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
Introduce an x86 interrupt stack frame that contains more information
than the non-debug one, namely the caller-saved GPRs, as well as an API
to retrieve it. Able to handle nested interrupts stack frames.
Change-Id: If182aaa2f34e4714b16ca65ff79da63b72d962f7
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
Allow a debug server such a GDB to take control when a fatal error
occurs. The debug server simply has to define a _debug_fatal_hook()
function that will override the weak function installed by default.
Change-Id: Ib9dca5755868f747b697fa3178e09109f1eedb07
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
It wasn't correct to add the size of the long jump instruction
as it *replaces* a short jump instead of just being after it.
So redefine this to be the difference in size between these
two instructions.
Change-Id: I65be2afab19d9cd8b096551acde0156f0503df87
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Changed names of Kconfig flags, variables, functions, files and
return codes consistent with names used in the RFC. Updated
relevant comments to match the changes.
Origin: Original
Change-Id: Ie7941032d7ad7af61fc02928f74538745e7966e8
Signed-off-by: Ramesh Thomas <ramesh.thomas@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The thread monitor allows to iterate over the thread context
structures for each existing thread (fiber/task) in the system.
Thread context structures do not expose thread entry information
directly. Although all the information can be scavenged from memory
stacks. Besides, accessing the information depends on the stack
implementation for each architecture.
By extending the tcs we allow a direct access to the thread
entry point and its parameters, only when thread monitor is
enabled.
It also allows a task to access its kernel task structure
through the first parameter of the thread.
This allows a debugger application to access the information directly
from the thread context structures list.
Change-Id: I0a435942b80eddffdf405016ac4056eb7aa1239c
Signed-off-by: Juan Manuel Cruz <juan.m.cruz.alcaraz@intel.com>
One of the tricks that GCC's stack protector does is to stick a
sentinel value on the stack at the beginning of the function, and
check if it is still there when the function is about to return.
However, since this function switches stacks that fails and we get
a stack protector exception before main() even starts.
Change-Id: I2acba8b8c822d7447d8e371bb72603f36e87f54b
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Rearrange the source code in order to place functions
depending on clflush support detection into the proper
section.
Removed dependency between CACHE_LINE_SIZE_DETECT and
CLFLUSH_INSTRUCTION_SUPPORTED or CONFIG_CLFLUSH_DETECT.
Change-Id: I62ba5199763ed16c71f1d2fa372f6cc99b303e6a
Signed-off-by: Dmitriy Korovkin <dmitriy.korovkin@windriver.com>
The app-facing interface for configuring interrupts was never
formally defined, instead it was defined separately for each arch
in their respective arch-specific header files. Occasionally these
would go out of sync.
Now there is a single irq.h header which defines this interface.
To avoid runtime overhead, these map to _arch_* implementations of
each that must be defined in headers pulled in by arch/cpu.h.
Change-Id: I69afbeff31fd07f981b5b291f3c427296b00a4ef
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
That implementation is not galileo-specific, but rather a generic way of
rebooting an x86 target. Needs SoC support.
Change-Id: I9c3374a8ab57a624d9d9b7090260c5b11fe4e773
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
This is part of an ongoing development of power management
support in zephyr. This implementation builds upon an existing
hook interface and adds more enhancements. This was tested
with reference implementations on quark_d2000 and quark_se.
Change-Id: I28092b7ec90ce1f1cc661cf99ca88708910c8eb2
Signed-off-by: Ramesh Thomas <ramesh.thomas@intel.com>
Renamed functions and labels used in power management code
according to coding convention. Only doing this to relevant
functions and not touching functions that will be removed in
future patches.
The stack used during resume would be necessary so
renamed that too.
Change-Id: I2f09a349b0f0fd6520c11b4cd73f4c8e1a13f100
Signed-off-by: Ramesh Thomas <ramesh.thomas@intel.com>
GlobalTss is not defined anywhere. This was originally designed
to be used by power management code to switch thread context to
kernel resume location. An alternative to this method would be
implemented.
Change-Id: I9ae14ba14f9573d8bd8579869cdee9cf85a5684a
Signed-off-by: Ramesh Thomas <ramesh.thomas@intel.com>
Modifications to timer drivers and interrupt setup, to manage
the tickless idle for the x86 architecture
Change-Id: Ie02d484b7e5636de6ea382ba2eeed57e704c8498
Signed-off-by: Sergio Rodriguez <sergio.sf.rodriguez@intel.com>
Looking at the IDT in a debugger is confusing, add a pretty-printing
function.
Change-Id: Iacc5e204e5d11e3e875c75ddf6d2e2e80b230299
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
It was, in a nutshell, wrong. Fortunately, the incorrectly
specified fields weren't being used by anything.
Change-Id: I0fa63fa16a267502744a7a2c82865c7de8b5446e
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
DEBUG isn't tied to any config option. Just use assertions.
Most of the time return values aren't being checked anyway.
Change-Id: I7457dcf00e18505bd6bcd98d46288545c03b5fbc
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Having priority levels 0 and 1 reserved on x86 due to implementation
details on how the CPU uses the vector table is confusing to users,
and makes it unnecessarily difficult to share drivers between arches.
Now on x86, priority levels 0 and 1 are available. Semantically, all
priority levels have had 2 subtracted from them.
It is no longer necessary to specify a priority level when the
vector itself is specified. If an IDT entry has a specific vector
associated with it, any priority argument is simply ignored.
In gen_idt, some simplifications have been made:
- The printed representation of a generated entry now fits on one line
- Some checks being done in validate_priority() were redundant, as
generate_interrupt_vector_bitmap() also ensures that there are
sufficient free vectors within a priority level.
Change-Id: I26669d8ee0a53f48fbc2283490a8c42d8b1daf8e
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
The argument to _common_dynamic_exc_handler() in the C domain
was still being set up the Sys V way. Arguments are popped off the
stack in reverse order, so _ExcEnt pushes *pEsf for arg 2, and then
the stub pushes the stub_num for Arg 1.
For IAMCU case, *pEsf is placed in EAX which is where argument 1
lives; static exception handlers take just one argument. However
since we're calling _common_dynamic_exc_handler we also need to
supply the stub_id, which we put in EDX (where arg 2 goes).
Rather than swapping things around at runtime the prototype for
_common_dynamic_exc_handler() is adjusted to fit the calling
convention in use.
Change-Id: Id43cbc3b86d90f941cea771678b2796ae5f1358d
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Adds logger support to iamcu core for the following features:
- context switch logger
- interrupt logger
- sleep logger
Change-Id: Icfbd5fa787633045ba2895e8c28b652c55575b86
Signed-off-by: Juan Manuel Cruz <juan.m.cruz.alcaraz@linux.intel.com>
The common stub code didn't prefix the arg to 'mov' with a
'$', causing the assembler to generate code which tries to
dereference the argument before sticking it in EAX.
Change-Id: I0e201f799565d9709e3969b82ae2eb3f93a78b3a
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
The ASM stub invoked by irq_offload() wasn't switching to the
interrupt stack.
Change-Id: I0c52092a50396aa892e71f0501bbda38395d7554
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
We don't normally need a runtime-mutable GDT; make it optional to
activate a second copy in RAM. Regardless of whether it is in RAM
or ROM, it can be accessed by the '_gdt' symbol.
Change-Id: I5ce955f4b8875eb60040917ceaacc07d7e5941ac
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
It's not a function and requires all its arguments to be build-time
constants. Make this more obvious to the end user to ease confusion.
Change-Id: I64107cf4d9db9f0e853026ce78e477060570fe6f
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Mostly SoC initialization and some kernel subsystems, but also some
device drivers like the interrupt controllers.
Change-Id: I8dc1844c33acd877c075b6b03558fdca6f87500b
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
This is the last step before obsoleting DEVICE_DEFINE() and
DEVICE_INIT_CONFIG_DEFINE().
Change-Id: Ica4257662969048083ab9839872b4b437b8b351b
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
Rename it to DEVICE_DEFINE() so that it fits in the 'device' namespace.
Change-Id: I3af3a39cf9154359b31d22729d0db9f710cd202b
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
Most systems have far less than 256 IRQ lines available, so
save some bytes in ROM by making this a config option.
On systems with MVIC, omit the table entirely as the mapping
is fixed.
The build cmd_gen_idt is slightly easier to read and will fail
immediately if any of the commands in the sequence error out.
Change-Id: I411f114557591e5cd96b618e6f79f97e8bedadf0
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Rename it to DEVICE_INIT_CONFIG_DEFINE(), because (a) it was not fitting
in any namespace and (b) it is not used to declare, but rather define a
object.
Change-Id: I1da5822f06b85a9fb024b5b184afd0ccc01012ec
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
This bitfield is only needed to find unused vectors in the IDT
for installing dynamic interrupts.
Change-Id: I34ecd330774a0e50f240b4396527682eded29627
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
It wasn't immediately clear in _execute_handler() that
enable_interrupts() didn't actually do anything if
CONFIG_NESTED_INTERRUPTS wasn't enabled.
If we are not using nested interrupts, perform small optimization
1) The call to disable interrupts isn't necessary as interrupts
are already disasbled
2) The check for !_nanokernel.nested in a couple places always
evaluates to true if nested interrupts aren't used
Change-Id: I7e66cee0466d03bc1172a572e19389accf6e0e62
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
The interrupt API has been redesigned:
- irq_connect() for dynamic interrupts renamed to irq_connect_dynamic().
It will be used in situations where the new static irq_connect()
won't work, i.e. the value of arguments can't be computed at build time
- a new API for static interrupts replaces irq_connect(). it is used
exactly the same way as its dynamic counterpart. The old static irq
macros will be removed
- Separate stub assembly files are no longer needed as the stubs are now
generated inline with irq_connect()
ReST documentation updated for the changed API. Some detail about the
IDT in ROM added, and an oblique reference to the internal-only
_irq_handler_set() API removed; we don't talk about internal APIs in
the official documentation.
Change-Id: I280519993da0e0fe671eb537a876f67de33d3cd4
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
On SysV ABI, the NANO_ESF parameter is passed in via the stack.
For IAMCU, this is instead expected to be in EAX.
_ExcEnter is currently using EAX to stash the return address of
the calling stub while it does a stack switch. Change it to use ECX
for this purpose, and if we are running with IAMCU place the
parameter in EAX instead of pushing it.
The output of the fault handler has been cleaned up a bit and it
now also includes the code segment.
Change-Id: I466e3990a26a1a82dd486f3d8af5395eab60b049
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This was never implemented on ARC/ARM and has been superseded
by irq_offload().
Some checks that were only done with CONFIG_LOAPIC_DEBUG fall
under the category of 'shouldn't ever happen' and have been
converted into assertions, instead of propagating return values
which are largely never checked.
Change-Id: I4eedca05bb7b384c4f3aa41a4f037f221f4a9cfe
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Changes the nanokernel stack API so that the timeout parameter must be
specified when invoking nano_isr_stack_pop(), nano_fiber_stack_pop(),
nano_task_stack_pop() and nano_stack_pop().
This obsoletes the following APIs:
nano_fiber_stack_pop_wait()
nano_task_stack_pop_wait()
nano_stack_pop_wait()
Note that even though the new API requires that the timeout parameter
be specified, there are currently only two acceptable values:
TICKS_NONE and TICKS_UNLIMITED
This nanokernel option does not support CONFIG_NANO_TIMEOUTS.
Change-Id: Ic7f16ee30c3534115ceffa19ef8591ecc5a79080
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
Changes the nanokernel LIFO API so that the timeout parameter must be
specified when invoking nano_isr_lifo_get(), nano_fiber_lifo_get(),
nano_task_lifo_get() and nano_lifo_get().
This obsoletes the following APIs:
nano_fiber_lifo_get_wait()
nano_fiber_lifo_get_wait_timeout()
nano_task_lifo_get_wait()
nano_task_lifo_get_wait_timeout()
nano_lifo_get_wait()
nano_lifo_get_wait_timeout()
Change-Id: Ie9f93e46da42ea33c32544c02ab1d70b893cc198
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
Changes the nanokernel semaphore API so that the timeout parameter must be
specified when invoking nano_isr_sem_take(), nano_fiber_sem_take(),
nano_task_sem_take() and nano_sem_take().
This obsoletes the following APIs:
nano_fiber_sem_take_wait()
nano_fiber_sem_take_wait_timeout()
nano_task_sem_take_wait()
nano_task_sem_take_wait_timeout()
nano_sem_take_wait()
nano_sem_take_wait_timeout()
Change-Id: If7a4bce1bd8ec8d6410d04f3c16ff1922ff0910e
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
Changes the nanokernel FIFO API so that the timeout parameter must be
specified when invoking nano_isr_fifo_get(), nano_fiber_fifo_get(),
nano_task_fifo_get() and nano_fifo_get().
This obsoletes the following APIs:
nano_fiber_fifo_get_wait()
nano_fiber_fifo_get_wait_timeout()
nano_task_fifo_get_wait()
nano_task_fifo_get_wait_timeout()
nano_fifo_get_wait()
nano_fifo_get_wait_timeout()
Change-Id: Icbd2909292f1ced0bad8a70a075478536a141ef2
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
The argument to 'lidt' is a chunk of memory with the base address
and limit of the IDT, and not the IDT itself. Horrible things
were happening when the IDT itself was being passed to this
instruction.
To be extra safe, disable interrupts while we modify the table
and subsequently reload it.
Change-Id: I9bf96f13a5f6e1be80d11bbfb9db3df1f2ed613a
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Add support for compilers conforming to the IAMCU calling convention
as documented by
https://github.com/hjl-tools/x86-psABI/wiki/iamcu-psABI-0.7.pdf
Change-Id: I6fd9d5bede0538b2049772e3850a5940c5dd911e
Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
All of these stubs at the end pop the stack and tell the LOAPIC
that we are at EOI. Put this in common code which falls through to
_IntExit(). Saves 8 bytes per static IRQ stub. There is also small
constant savings in the common code for dynamic IRQs.
Change-Id: If17e9f105928a4251a2cb3fc0d192649c1c4d84b
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
The APIC by default uses vector 0xFF for the spurious interrupt
vector as described in the x86 CPU manual volume 3 section 10.9.
Make this its own config option defaulting to 32.
MVIC doesn't have a spurious interrupt vector, and due to the
fixed IRQ-to-vector mapping for this controller, continue
to use the last available entry.
Change-Id: I29bd09df700629dc0d15b30a6ae590b0df1ef890
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Peter Mitsis