Commit Graph

21 Commits

Author SHA1 Message Date
Kumar Gala a1b77fd589 zephyr: replace zephyr integer types with C99 types
git grep -l 'u\(8\|16\|32\|64\)_t' | \
		xargs sed -i "s/u\(8\|16\|32\|64\)_t/uint\1_t/g"
	git grep -l 's\(8\|16\|32\|64\)_t' | \
		xargs sed -i "s/s\(8\|16\|32\|64\)_t/int\1_t/g"

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-06-08 08:23:57 -05:00
Peter Bigot cbe207377e drivers: gpio_dw: add support for pin validation
Add the common config structure as a prefix of the driver-specific
config structure and use the devicetree GPIO pin counts to initialize
it.

Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
2020-02-05 12:00:36 +01:00
Kumar Gala bcdc057503 drivers: gpio_dw: Add gpio_driver_data to driver data
Add gpio_driver_data as the first element in the driver data as the gpio
core expects this.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-02-05 12:00:36 +01:00
Charles E. Youse 68f45fd6d4 drivers/gpio/gpio_dw: remove support for legacy PCI interface
Only Quark SoCs used this IP block hanging off a PCI bus, and the PCI
support is written for the deprecated legacy PCI subsystem, so remove.

Signed-off-by: Charles E. Youse <charles.youse@intel.com>
2019-09-08 22:09:10 -04:00
Anas Nashif 6aa9c3a68f cleanup: include/: move gpio.h to drivers/gpio.h
move gpio.h to drivers/gpio.h and
create a shim for backward-compatibility.

No functional changes to the headers.
A warning in the shim can be controlled with CONFIG_COMPAT_INCLUDES.

Related to #16539

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2019-06-27 22:55:49 -04:00
Flavio Ceolin 67ca176754 headers: Fix headers across the project
Any word started with underscore followed by and uppercase letter or a
second underscore is a reserved word according with C99.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2018-09-17 15:49:26 -04:00
Kumar Gala ccad5bf3e3 drivers: convert to using newly introduced integer sized types
Convert code to use u{8,16,32,64}_t and s{8,16,32,64}_t instead of C99
integer types.

Jira: ZEP-2051

Change-Id: I08f51e2bfd475f6245771c1bd2df7ffc744c48c4
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-04-21 10:06:48 -05:00
Kumar Gala 789081673f Introduce new sized integer typedefs
This is a start to move away from the C99 {u}int{8,16,32,64}_t types to
Zephyr defined u{8,16,32,64}_t and s{8,16,32,64}_t.  This allows Zephyr
to define the sized types in a consistent manor across all the
architectures we support and not conflict with what various compilers
and libc might do with regards to the C99 types.

We introduce <zephyr/types.h> as part of this and have it include
<stdint.h> for now until we transition all the code away from the C99
types.

We go with u{8,16,32,64}_t and s{8,16,32,64}_t as there are some
existing variables defined u8 & u16 as well as to be consistent with
Zephyr naming conventions.

Jira: ZEP-2051

Change-Id: I451fed0623b029d65866622e478225dfab2c0ca8
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-04-20 16:07:08 +00:00
David B. Kinder ac74d8b652 license: Replace Apache boilerplate with SPDX tag
Replace the existing Apache 2.0 boilerplate header with an SPDX tag
throughout the zephyr code tree. This patch was generated via a
script run over the master branch.

Also updated doc/porting/application.rst that had a dependency on
line numbers in a literal include.

Manually updated subsys/logging/sys_log.c that had a malformed
header in the original file.  Also cleanup several cases that already
had a SPDX tag and we either got a duplicate or missed updating.

Jira: ZEP-1457

Change-Id: I6131a1d4ee0e58f5b938300c2d2fc77d2e69572c
Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-01-19 03:50:58 +00:00
Vincenzo Frascino add1b55dca gpio: Cleanup DW gpio driver
This patch addresses the following issues:
* Aligns the Kconfig code style with Zephyr projects requirements.
* Removes redundant "depends on" from Kconfig.
* Adds static to the gpio_dw_isr declaration.
* Adds guards to the header files.

Change-Id: I1ae70868f0bda97891cbeb494e5efba1bd537aa1
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@linaro.org>
2016-11-16 17:18:01 +00:00
Marcus Shawcroft 27f4947812 driver/gpio/dw: Limit name space, add static.
Change-Id: I3b1f5497896f683072c2bc473d348cd19aca3c5d
Signed-off-by: Marcus Shawcroft <marcus.shawcroft@arm.com>
2016-10-26 20:51:06 +00:00
Marcus Shawcroft 8564334254 gpio/dw: Move RW objects in config_info to driver_data
PCI enumeration modifies pci_dev and base_addr at driver
initialization therefore these objects move from config_info to
driver_data in preparation for config_info becoming const.

We drop code that attempts to update irq_num based on PCI enumeration
because the interrupt found by PCI enumeration must always be the same
as the statically configured IRQ number.

Change-Id: Ibfefa851d2836d524b8151ed0108ecf9de2cd3a3
Signed-off-by: Marcus Shawcroft <marcus.shawcroft@arm.com>
2016-10-19 12:10:58 +00:00
amirkapl c490219d1e power_mgmt: Update sample and drivers according to new pm device API
Update the power sample and drivers with the new device driver power
management API using the existing logic

Jira: ZEP-954
Change-Id: Idd94232e458767635973e94e9fc673c01612c1e2
Signed-off-by: Amir Kaplan <amir.kaplan@intel.com>
2016-09-22 00:23:43 +00:00
Chuck Jordan c1e4bcf996 gpio: For ARC EM Starterkit, a 4-port GPIO implementation is being added
The file gpio_dw_registers.h already had the 4-port GPIO
registers defined, yet the gpio_dw.c implementation didn't
support it properly. There are 4 ports here, not 2, and only
PORTA can support interrupts and debounce.

On the em_starterkit board, for example, PORTA
has 3 bits for buttons: A, L and R. The other 3 ports should not
be used with interrupts & debounce.

I've re-worked this file to derive the port number from the
base address given. The lower 6 bits are divided by 12 to
derive the port number. From this, the registers EXT_PORTA,
EXT_PORTB, EXT_PORTC or EXT_PORTD can be read.

Also, for those ports that don't support interrupts,
set irq_num to 0, and that code will be avoided. I've verified
that I can access GPIO now correctly on the EM Starterkit. The
em_starterkit board support will be submitted soon but I'm
staging in this change first.

Change-Id: I98dbe083e03e046b40e07b4b14a99a39a6d0f0be
Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
2016-05-26 00:10:42 +00:00
Tomasz Bursztyka fea1c49ba2 gpio: Improve the public API to handle multi callbacks
Many sub-systems might require to set a callback on different pins.
Thus enabling it via changing the API.

It is also possible to retrieve private-data in the callback handler
using CONTAINER_OF() macro (include/misc/util.h).

Former API is still available, and is emulated through the new one.
Using both should not be a problem as it's using new API calls.
However, it's now better to start using the new API.

Change-Id: Id16594202905976cc524775d1cd3592b54a84514
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2016-04-22 22:15:12 -04:00
Peter Mitsis a0e4568760 c++: Add extern "C" { } block to header files
Adds extern "C" { } blocks to header files so that they can be
safely used by C++ source files.

Change-Id: Ia4db0c36a5dac5d3de351184a297d2af0df64532
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
2016-02-05 20:25:22 -05:00
Anas Nashif cf81e1ff87 gpio: gpio_dw_registers.h is local to the file including it
Change-Id: I501a6fd2239511d46236fade47fc41d69093471d
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:25:04 -05:00
Tomasz Bursztyka 8e4aff1079 gpio: dw: Support optional clock gating
This is currently valid for quark_se platform. It's used internally to
suspend and/or resume the gpio controller.

Change-Id: I5147568ba6b0450363566b5f9fd2e8aa7e41df49
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2016-02-05 20:24:55 -05:00
Juan Manuel Cruz 59cb73520a gpio: adds gpio dw register support for ss quark se
Adds the register definition for the DW GPIO hardware block.
This set of registers and offsets are specific for the SS
GPIO hardware block in the Quark SE platform.
In particular, the register BOTHEDGE (offset 0x68 in the
main GPIO block) does not exist on the SS GPIO block.

Change-Id: I4e16ec7c8e89015be1fc8bcdb1b7fa5377890b9d
Signed-off-by: Juan Manuel Cruz <juan.m.cruz.alcaraz@linux.intel.com>
2016-02-05 20:24:48 -05:00
Anas Nashif c159380c86 gpio: make function names conform to driver name
use gpio_dw instead of gpio_<function>_dw to be consistent in the
driver itself and with other drivers.

Change-Id: Ifb0e50c230f142197eb4b01c1bb4ce1c16e4753f
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:24:41 -05:00
Dan Kalowsky 6bf971915f gpio: rename files
The naming convention used in the source is for there to be an
_ and not a - in the file.  Fixing GPIO to be consistent with
the os naming conventions.

Change-Id: Ifc4356c14b52e2cc2411a7445b44c7cb57d2765c
Signed-off-by: Dan Kalowsky <daniel.kalowsky@intel.com>
2016-02-05 20:24:31 -05:00