The FPGA on the MPS2 board implements 4 SBCon devices for I2C which are
connected to:
- a touchscreen controller
- the audio device (for configuration)
- both shield connectors
Change-Id: I55ca985e18b45d68f5e7421c4768dfc9bf2fcb3f
Signed-off-by: Jon Medhurst <tixy@linaro.org>
Introduce a simple device tree for the TI lm3s6965 SoC and QEMU
Cortex-M3 board port. We get flash and memory base addresses and sizes
from the device tree as well as the ARM NVIC number of priority bits.
Change-Id: I4452b5543de7be55518997e54837ccbfd4f121df
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
As disco_l475_iot1 is default board for HTS221 sample
application, provide default boards settings to get
application functional once it is delivered.
Change-Id: Ie4957538db679d076713550c1555954a6a20d3e2
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add device tree support for nRF51822 SoCs and Arduino 101-BLE,
Curie-BLE, BLE Nano, PCA10028-DK, and Quark-SE BLE boards. This
is minimal support for memory, flash, and UART.
Change-Id: I7e572bea537e384b6d66e520462f023ace0c9b35
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Add device tree support for nRF52840 SoC and PCA10056-DK board. This
is minimal support for memory, flash, and UART.
For the nRF52840 we select between "nordic,nrf-uarte", "nordic,nrf-uart"
support for each board.
Change-Id: I1c377e0cb97ff4716ea5489fffaa7c0e2b34d18a
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Add device tree support for Nitrogen 96board, BLE Nano 2, and
nRF52-PCA10040 DK boards. This is minimal support for memory, flash,
and UART.
For the nRF52832 we select between "nordic,nrf-uarte", "nordic,nrf-uart"
support for each board.
Change-Id: Ia247b9b710a72416e9ab0de3ca1429bfab8917f8
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit provides support for disco_l475_iot1 board
Pinmux driver is provided with initial support definitions
Change-Id: I17b637a8ba0b033014969eca8fffe76319c47c52
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
In order to allow the use of such board, a very preliminar port was
developed. It consists of board files, as well as pinmux, uart, gpio,
spi drivers and device tree files.
Change-Id: I5753064e39e0b023cf4481744c176de26d8dbebb
Signed-off-by: Gustavo Denardin <gustavo.denardin@gmail.com>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commits align CONFIG_ factor names between stm32f4 and stm32l4
series to enable code factorization such as use of Q_DIVISOR.
Though, it does not concatenate kconfig sections as we might use
a bit of time to see what is needed in this regard
Change-Id: Ia603406d53949abf5675b801a5448397d5ab8462
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Following activation of stm32 common clock driver for stm32f4 series
remove references to stm32f4 specific driver.
Change-Id: I372a0ea046007bcb34944d6b2b8880077583b1d3
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This commit provides CONFIG_ definitions to support
LL based clock driver on stm32f4 boards:
96b_carbon
nucleo_f401re
nucleo_f411re
This commit sticks to clock configurations previously defined.
Two changes to notice:
-HSE clock value should now be defined
-Prescaler values required as "1" should now be set to "1" instead
of "0".
Change-Id: I003bd226f198217d5e266e11fe37094773c1c62c
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Added some review changes suggested by TI-er Bill Mills.
Jira: ZEP-1958
Change-Id: I892f22a5740ae7ae4dc949bc72de366e0e85d03c
Signed-off-by: Gil Pitney <gil.pitney@linaro.org>
This board is being replaced by the CC3220SF LaunchXL,
which has essentially the same peripheral map, 256Kb
of SRAM, but in addition has 1Mb of on-chip secure flash.
Jira: ZEP-1958
Change-Id: I80629474cab9ce41bce3903213f5c9f148cc138a
Signed-off-by: Gil Pitney <gil.pitney@linaro.org>
CC3220SF_LAUNCHXL effectively replaces the CC3200_LAUNCHXL,
with support for the CC3220SF SoC, which is an update for
the CC3200 SoC.
This is supported by the Texas Instruments CC3220 SDK.
Jira: ZEP-1958
Change-Id: I2484d3ee87b7f909c783597d95128f2b45db36f2
Signed-off-by: Gil Pitney <gil.pitney@linaro.org>
Adds event based scheduling logic to the kernel. Updates
management of timeouts, timers, idling etc. based on
time tracked at events rather than periodic ticks. Provides
interfaces for timers to announce and get next timer expiry
based on kernel scheduling decisions involving time slicing
of threads, timeouts and idling. Uses wall time units instead
of ticks in all scheduling activities.
The implementation involves changes in the following areas
1. Management of time in wall units like ms/us instead of ticks
The existing implementation already had an option to configure
number of ticks in a second. The new implementation builds on
top of that feature and provides option to set the size of the
scheduling granurality to mili seconds or micro seconds. This
allows most of the current implementation to be reused. Due to
this re-use and co-existence with tick based kernel, the names
of variables may contain the word "tick". However, in the
tickless kernel implementation, it represents the currently
configured time unit, which would be be mili seconds or
micro seconds. The APIs that take time as a parameter are not
impacted and they continue to pass time in mili seconds.
2. Timers would not be programmed in periodic mode
generating ticks. Instead they would be programmed in one
shot mode to generate events at the time the kernel scheduler
needs to gain control for its scheduling activities like
timers, timeouts, time slicing, idling etc.
3. The scheduler provides interfaces that the timer drivers
use to announce elapsed time and get the next time the scheduler
needs a timer event. It is possible that the scheduler may not
need another timer event, in which case the system would wait
for a non-timer event to wake it up if it is idling.
4. New APIs are defined to be implemented by timer drivers. Also
they need to handler timer events differently. These changes
have been done in the HPET timer driver. In future other timers
that support tickles kernel should implement these APIs as well.
These APIs are to re-program the timer, update and announce
elapsed time.
5. Philosopher and timer_api applications have been enabled to
test tickless kernel. Separate configuration files are created
which define the necessary CONFIG flags. Run these apps using
following command
make pristine && make BOARD=qemu_x86 CONF_FILE=prj_tickless.conf qemu
Jira: ZEP-339 ZEP-1946 ZEP-948
Change-Id: I7d950c31bf1ff929a9066fad42c2f0559a2e5983
Signed-off-by: Ramesh Thomas <ramesh.thomas@intel.com>
Typo in :ref:`hello_world` (regular quote vs. back tick)
Change-Id: I77853f85b9c71751307ef105b6babcb0cfbc9060
Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
This patch adds MPU support to the ST nucleo_f411re board based on
STM32F401XE.
Change-Id: I43aae0930ccabe234fcb34216518b568a855a1be
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@linaro.org>
This patch adds MPU support to the ST nucleo_f401re board based on
STM32F401XE.
Change-Id: I5e8042c1f964827980b974a565a4d4666eeccf3b
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@linaro.org>
This patch adds MPU support to the 96 boards Carbon board based on
STM32F401XE.
Change-Id: I8444318099a665133488ccdd5ba129c805f9a20e
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@linaro.org>
This patch enables MPU by default into the V2M Beetle port of Zephyr.
Change-Id: Iab2dea748c68a6932eb31e746d1a9cdb07808683
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@linaro.org>
The current PLL settings for the Carbon have two problems.
1. The VCO frequency (672MHz) is out of spec.
2. The 48MHz clock is being driven at 84MHz which breaks USB,
breaks SDIO and also risks biasing the RNG.
Fix this by bringing the VCO down to 336MHz (which also fixes
the 48MHz clock) and update the other dividers accordingly.
Change-Id: I394c476a8b27f027da5cdc31992613b376cf6aff
Signed-off-by: Daniel Thompson <daniel.thompson@linaro.org>
Convert code to use u{8,16,32,64}_t and s{8,16,32,64}_t instead of C99
integer types.
Jira: ZEP-2051
Change-Id: I27d51c316144251939b20cfa6787ff7ab8035fe6
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Fix doxygen comment typos used to generate API docs
Change-Id: I248d53000d8e57b902b9a18fdcfc9e995142a8b3
Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
Added serial (UART) driver for Atmel SAM MCU family.
Note:
- Error handling is not implemented
- The driver works only in polling mode, interrupt mode is
not implemented.
Tested on Atmel SMART SAM E70 Xplained board
Origin: Original
Jira: ZEP-1959
Change-Id: I3e770fd1feb2ddf92cf405a9aa17be92eb32e19b
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
Added I2C bus (TWIHS) driver for Atmel SAM MCU family. Only
I2C Master Mode with 7 bit addressing is currently supported.
Tested on Atmel SMART SAM E70 Xplained board
Origin: Original
Jira: ZEP-1866
Change-Id: Ic5aa7b6b21295feccae883d580b38bbeaf2ce291
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
CONFIG_BOARD was set to arduino_101_ble instead of curie_ble. Fix this
so the BOARD_NAME, BOARD, board dir, all are in sync.
Change-Id: I5f2a4f1aeec7c20f042e11b96e1c87883ad4df4b
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Introduce SoC specific config options similar to what exists on NRF51,
this is mostly to help distinguish between SRAM & Flash sizes on
different variants.
Also deleted some unnecessary setting of CONFIG_SOC_NRF528{32,40} in the
board defconfig files.
Change-Id: I3aaedf0c15423ae12636f87b8e6a39070cbb2c6f
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Adds initial support and documentation for the kw40z on the hexiwear
board.
Jira: ZEP-1391
Change-Id: Idb58bfb3c2951b1f737a8c547860bde4ef4d9a3e
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Converted over all STM32F3 based boards to use device tree and removed
associated bits that now come from the device tree for STM32F3.
Boards that are now using devicetree:
* Nucleo f334r8
* STM32373C Eval
Change-Id: I081a1d83f86e417a98b6864c745354b6b32953b7
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Converted over all STM32F1 based boards to use device tree and removed
associated bits that now come from the device tree for STM32F1. Also
renamed the STM32F10{3,7} SoC dtsi to try and make it clear that the 'X'
is a place holder. Fixedup the top level compatiables in the boards to
be the specific 'X' instead of the generic one.
Boards that are now using devicetree:
* Nucleo f103rb
* STM3210C Eval
* STM32 MINI A15
Change-Id: I29b3634ec7451f974687d55980414efa655e2e96
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Converted over all STM32F4 based boards to use device tree and removed
associated bits that now come from the device tree for STM32F4.
Boards that are now using devicetree:
* 96b_carbon
* nucleo f401re
* nucleo f411re
Change-Id: Ibe197ca0a3f5ad78d594485a578d986403cc824a
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Since all the L4 SoCs are using DTS we can remove the various Kconfig
bits that we now get from DTS.
Change-Id: Icdec49b478ff285dc3347b09412964a721f75bbf
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
I2C_SHARED_IRQ, I2C_0_IRQ_SHARED, I2C_0_IRQ_DIRECT Kconfig options
are DW driver specific. Its presence is confusing for a user of any
other I2C driver than DW. This patch renames these options to include
DW string and makes it visible only for DW I2C driver. This is a
similar implementation to that used by ETH DW Ethernet driver.
Change-Id: I795506f9b103c028a22317df9ad632dce5cd1343
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
By default a factory new SAM E70 chip will boot SAM-BA boot loader located in
the ROM, not the flashed image. This is determined by the value of GPNVM1
(General-Purpose NVM bit 1). Updated flash procedure will ensure that GPNVM1
is set to 1 changing the default behavior to boot from Flash.
Change-Id: Ic6334c9d4743a7665fc944e8f49fc1467ecda40d
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
Add openocd.cfg to control flashing and debugging of the
olimexino-stm32 board
Change-Id: Ia40d964b737792864efd85076bc599b2de15ebb0
Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
The schematics of the BBC micro:bit are hard to find, and its official
web-site doesn't document the mapping of the edge connector pins
numbers the nRF51 GPIO pin numbers. Provide helpful defines for this
in the board.h file.
Change-Id: I52ce1d61558703b6aa5a5d073ccd222f27fa8760
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
The core build in the SDK does not have a timer, making it impossible
to use this core with most of the sanity checks. We are working on
getting a special package of cores for Zephyr which meet our build
requirments; until then, remove this core as it doesn't build.
Change-Id: I3fa201f3c6b5724501e8cb1e1b8ba631436ebc23
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
* CONFIG_SOC is now properly set and we do not need a separate
XTENSA_CORE build variable
* Some unnecessary macro -D CFLAGS in the Xtensa Makefile removed
* There is no default SOC selection, it is now done explicitly in
the board's defconfig
* CONFIG_<board name> now renamed to CONFIG_SOC_<board name in
uppercase> to conform to established style.
Issue: ZEP-1711
Change-Id: I88997530db09970b7fdd1c3e3d355bfca9d0be1a
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Jon Medhurst