1. Replace the non-existent CPU device binding ("Cortex-R") specified
by the CPU node with a proper one.
2. Relocate CPU node declaration to SoC dtsi:
The CPU node should be declared in the SoC dtsi because the core
type is SoC-dependent. In fact, this is exactly how it is done in
the Cortex-M port.
3. Remove core_intc (supposedly Cortex-R VIC):
Unlike the NVIC of Cortex-M, the VIC of Cortex-R is not a true
interrupt controller in the conventional sense and merely acts as
a CPU input port for aggregated interrupt request and vector index
signals. For this reason, there is no point in declaring it in the
device tree and specifying it as an interrupt parent. All SoCs
incorporating Cortex-R implement a separate true interrupt
controller (for instance, GIC for Zynq MPSoC and VIM for Hercules).
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
'interrupt-parent' should contain just the phandle of the node
interrupts are sent to.
This node (gic: interrupt-controller@f9010000) doesn't generate any
interrupts, so the 'interrupt-parent' value is never used (this is why
it wasn't caught). It'll give an error later with 'interrupt-parent'
declared as 'type: phandle' in bindings though.
Don't know what was intended. Just remove the 0.
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
This commit adds support for the Zynq UltraScale+ MPSoC as a qemu based
platform for Cortex-R based testing. This SoC only supports an
interrupt controller and serial port for limited testing.
Signed-off-by: Bradley Bolen <bbolen@lexmark.com>
Stephanos Ioannidis