Commit Graph

21 Commits

Author SHA1 Message Date
Carlo Caione 3539c2fbb3 arm/arm64: Make ARM64 a standalone architecture
Split ARM and ARM64 architectures.

Details:

- CONFIG_ARM64 is decoupled from CONFIG_ARM (not a subset anymore)
- Arch and include AArch64 files are in a dedicated directory
  (arch/arm64 and include/arch/arm64)
- AArch64 boards and SoC are moved to soc/arm64 and boards/arm64
- AArch64-specific DTS files are moved to dts/arm64
- The A72 support for the bcm_vk/viper board is moved in the
  boards/bcm_vk/viper directory

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2021-03-31 10:34:33 -05:00
Raveendra Padasalagi 206f341a51 soc: arm: bcm_vk: viper: Increase default NUM_IRQS
Maximum GIC SPI is 228, so maximum INTID is 228 + 32 = 260.
So, _sw_isr_table needs to support 260 entries

Signed-off-by: Raveendra Padasalagi <raveendra.padasalagi@broadcom.com>
Signed-off-by: Abhishek Shah <abhishek.shah@broadcom.com>
2021-03-05 07:21:54 -06:00
Raveendra Padasalagi 8c704ea3a8 soc: viper: update registers and interrupt numbers
Update register addresses and NVIC/GIC interrupt numbers
according to the latest viper RTL version.

Signed-off-by: Raveendra Padasalagi <raveendra.padasalagi@broadcom.com>
Signed-off-by: Abhishek Shah <abhishek.shah@broadcom.com>
2021-03-05 07:21:54 -06:00
Carlo Caione 9d908c78fa aarch64: Rewrite reset code using C
There is no strict reason to use assembly for the reset routine. Move as
much code as possible to C code using the proper helpers.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2021-03-04 06:51:48 -05:00
Carlo Caione a2226f5200 aarch64: Fix registers naming in cpu.h
The name for registers and bit-field in the cpu.h file is incoherent and
messy. Refactor the whole file using the proper suffixes for bits,
shifts and masks.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2021-03-04 06:51:48 -05:00
Carlo Caione 7b7c328f7a aarch64: mmu: Enable support for unprivileged EL0
The current MMU code is assuming that both kernel and threads are both
running in EL1, not supporting EL0. Extend the support to EL0 by adding
the missing attribute to mirror the access / execute permissions to EL0.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2020-11-04 13:58:19 -08:00
Abhishek Shah b53f62d259 drivers: pcie_ep: iproc: Add MSI-X PVM feature for Viper
Add support for interrupt driven MSI-X PVM feature for Viper.
Function mask bit update is tracked with snoop interrupt
and vector mask bit update is tracked with pcie pmon lite
address range access detection interrupt.
Both the interrupts are required to enable this feature.

Signed-off-by: Abhishek Shah <abhishek.shah@broadcom.com>
2020-10-22 11:07:39 +02:00
Tomasz Bursztyka e18fcbba5a device: Const-ify all device driver instance pointers
Now that device_api attribute is unmodified at runtime, as well as all
the other attributes, it is possible to switch all device driver
instance to be constant.

A coccinelle rule is used for this:

@r_const_dev_1
  disable optional_qualifier
@
@@
-struct device *
+const struct device *

@r_const_dev_2
 disable optional_qualifier
@
@@
-struct device * const
+const struct device *

Fixes #27399

Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2020-09-02 13:48:13 +02:00
Abhishek Shah 3a63e8564e soc: arm: viper: Fix callee saved register corruption in el3 init
x19 is callee saved register. z_arch_el3_plat_init being a callee,
it should save it before using it. However, at this point, stack
has not been setup. So, let's just use x20 instead which is not
being used caller yet. This bug was causing VBAR_EL1 corruption,
but since [10:0] bits are reserved, bug was hidden.

Signed-off-by: Abhishek Shah <abhishek.shah@broadcom.com>
2020-07-13 11:53:36 +02:00
Abhishek Shah 585d6d806c soc: arm: viper: Add PCIe highmem OB memory in MMU table
Add and mark PCIe highmem outbound memory as nGnRnE device memory
in Viper SoC MMU configuration.
Increase VA/PA bits to 36-bits to support the same.

Signed-off-by: Abhishek Shah <abhishek.shah@broadcom.com>
2020-07-07 15:07:51 +02:00
Abhishek Shah 7d587abc6e drivers: pcie: ep: iproc: Add reset interrupt handlers
Add reset interrupt handlers for all three types of reset
interrupts that iProc PCIe EP can receive - namely PERST,
INB PERST and FLR.

Signed-off-by: Shivaraj Shetty <shivaraj.shetty@broadcom.com>
Signed-off-by: Abhishek Shah <abhishek.shah@broadcom.com>
2020-06-22 12:44:54 +02:00
Stephanos Ioannidis 9cf4cab53d soc: arm: Fix header inclusion from deprecated paths
This commit fixes Cortex-M header inclusions from the deprecated paths.

The Cortex-M headers were relocated from `include/arch/arm/cortex_m` to
`include/arch/arm/aarch32/cortex_m` by the refactoring done in the
commit d048faacf2.

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2020-06-09 10:38:36 +02:00
Kumar Gala a1b77fd589 zephyr: replace zephyr integer types with C99 types
git grep -l 'u\(8\|16\|32\|64\)_t' | \
		xargs sed -i "s/u\(8\|16\|32\|64\)_t/uint\1_t/g"
	git grep -l 's\(8\|16\|32\|64\)_t' | \
		xargs sed -i "s/s\(8\|16\|32\|64\)_t/int\1_t/g"

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-06-08 08:23:57 -05:00
Sandeep Tripathy a515934a4b plat: bcm_vk: core specific init
Add initilizations for:
- Cortex-A72 L2 Controller configurations. This initialization to
 be done when cluster is in quiscent state.
- 'ICC_SRE_EL3' init to allow GIC V3 ICC_SRE_ELx system interface.
 This initialization can be done at 'EL3' only.

Signed-off-by: Sandeep Tripathy <sandeep.tripathy@broadcom.com>
2020-05-09 12:23:40 +02:00
Arjun Jyothi d18ae2e9fb soc: arm: Add Broadcom Viper SoC support
Add initial support for Broadcom Viper SoC.
It has ARM Cortex-M7 and Cortex-A72 cores.

Signed-off-by: Arjun Jyothi <arjun.jyothi@broadcom.com>
Signed-off-by: Abhishek Shah <abhishek.shah@broadcom.com>
2020-05-08 10:46:23 +02:00
Kumar Gala fbdeda9df2 dts: arm: remove DT_NUM_IRQ_PRIO_BITS and DT_NUM_MPU_REGIONS
We don't need to define DT_NUM_IRQ_PRIO_BITS or DT_NUM_MPU_REGIONS in
dts_fixup.h files anymore, so we can remove them.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-04-17 15:17:43 +02:00
Kumar Gala 5648df39ac arch: arm: cortex_m: Rework DT_NUM_IRQ_PRIO_BITS
To remove the need to have DT_NUM_IRQ_PRIO_BITS defined in every
dts_fixup.h we can just handle the few variant cases in irq.h.  This
allows us to remove DT_NUM_MPU_REGIONS from all the dts_fixup.h files.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-04-17 15:17:43 +02:00
Timo Teräs 6fd168e9a1 driver: uart: ns16550: convert to DT_INST_*
Change to code to use the automatically generated DT_INST_*
defines and remove the now unneeded configs and fixups.

Signed-off-by: Timo Teräs <timo.teras@iki.fi>
2020-03-14 02:22:05 +02:00
Ulf Magnusson a42a42cd5a kconfig: Replace defconfig singe-symbol 'if's with 'depends on'
Same deal as in commit eddd98f ("kconfig: Replace some single-symbol
'if's with 'depends on'"), for all symbols defined within defconfig
files. See that commit for an explanation.

Maybe 'if's were used originally to mirror the 'if's in the main Kconfig
files, and then it got copied around by people assuming 'if' must work
differently from 'depends on'. It doesn't match in every spot at least.
Better to keep it simple and just consistently use 'depends on' when
it's a single symbol/choice I think. Helps reinforce that 'if' isn't
magic too.

Verified by printing all Kconfig menu nodes (symbols, choices, menus,
etc.) before and after the change and diffing (should show no
difference).

Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
2020-02-12 10:32:13 -06:00
Ulf Magnusson c5839f834b kconfig: Remove assignments to CONFIG_<arch> syms and hide them
All board defconfig files currently set the architecture in addition to
the board and the SoC, by setting e.g. CONFIG_ARM=y. This spams up
defconfig files.

CONFIG_<arch> symbols currently being set in configuration files also
means that they are configurable (can be changed in menuconfig and in
configuration files), even though changing the architecture won't work,
since other things get set from -DBOARD=<board>. Many boards also allow
changing the architecture symbols independently from the SoC symbols,
which doesn't make sense.

Get rid of all assignments to CONFIG_<arch> symbols and clean up the
relationships between symbols and the configuration interface, like
this:

1. Remove the choice with the CONFIG_<arch> symbols in arch/Kconfig and
   turn the CONFIG_<arch> symbols into invisible
   (promptless/nonconfigurable) symbols instead.

   Getting rid of the choice allows the symbols to be 'select'ed (choice
   symbols don't support 'select').

2. Select the right CONFIG_<arch> symbol from the SOC_SERIES_* symbols.
   This makes sense since you know the architecture if you know the SoC.

   Put the select on the SOC_* symbol instead for boards that don't have
   a SOC_SERIES_*.

3. Remove all assignments to CONFIG_<arch> symbols. The assignments
   would generate errors now, since the symbols are promptless.

The change was done by grepping for assignments to CONFIG_<arch>
symbols, finding the SOC_SERIES_* (or SOC_*) symbol being set in the
same defconfig file, and putting a 'select' on it instead.

See
https://github.com/ulfalizer/zephyr/commits/hide-arch-syms-unsquashed
for a split-up version of this commit, which will make it easier to see
how stuff was done. This needs to go in as one commit though.

This change is safer than it might seem re. outstanding PRs, because any
assignment to CONFIG_<arch> symbols generates an error now, making
outdated stuff easy to catch.

Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
2020-02-08 00:50:08 -06:00
Scott Branden 54ce0b2d34 arm: Add Broadcom Valkyrie SoC support
Add initial support for Broadcom Valkyrie SoC as part of Zephyr.

Signed-off-by: Scott Branden <scott.branden@broadcom.com>
2020-01-30 03:54:01 -06:00