This commit includes the following:
1. Add symbol for choice option. So we can override the default value
by an earlier definition.
2. NPCX9 doesn't support 33MHz SPI clock in the header. So disable the
option for NPCX9.
3. NPCX9 support 512K flash. Change default to 512k for NPCX9.
Signed-off-by: Wealian Liao <WHLIAO@nuvoton.com>
To be able to get a tokenize DT string without the quotes. Deprecate
also DT_ENUM_TOKEN and DT_ENUM_UPPER_TOKEN.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Default Voltage scaling range selection (range2)
doesn't allow to configure Max frequency
switch to range1 to match any frequency
Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
Default Voltage scaling range selection (range2)
doesn't allow to configure Max frequency
switch to range1 to match any frequency
Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
Add power management support (runtime-idle and suspend-to-idle)
support for the NXP Kinetis KE1xf SoC series.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Enable the NXP Kinetis Low Power Timer (LPTMR) OS timer driver when
power management is enabled as the Arm SysTick timer cannot wake up the
KE1xF from deep sleep.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Keep the Slow Internal Reference Clock (SIRC) running in low-power
mode.
This allows peripherals that needs to remain operative in low-power
mode to use the SIRC as clock source.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Determine the default CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC from devicetree
when using the Arm SysTick hardware timer.
When the NXP KE1xF SoC series is using the Arm SysTick as hardware
timer, the cycles/second will always be equal to the CPU core clock
frequency.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Adds a devicetree chosen node to the mimxrt1170_evk_cm7 board to link
Segger RTT and SystemView sections in DTCM by default. Enables the AHB
clock while the CM7 is sleeping to allow debug access to the TCM.
Note that automatic RTT control block detection may not search the DTCM
address region, therefore you may need to manually set the RTT control
block address or search range in the Segger host tools (SystemView or
RTT Viewer). For example,
$ JLinkRTTViewer -ra 0x20000000
Tested with:
- samples/subsys/shell/shell_module/
- samples/subsys/tracing/
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
The SoC driver name is 'USB High-Speed Interface (USBHS)'. This rename
from usb_dc_sam to usb_dc_sam_usbhs allowing add others SoC drivers
like 'USB Device Port (UDP)' that is found at SAM4S/E variations.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
This commit adds support for stm32wle4xx, stm32wle5xx single core socs,
as well as stm32wl54 dual core soc.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
The bootloader itself contains the i.MX RT6xx boot header, so we don't
need to duplicate it when building chainloaded applications.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Refactors the i.MX RT600 SoC series to be more consistent with the i.MX
RT10xx SoC series by choosing a child node (external flash device) of
the FlexSPI bus for zephyr,flash.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
This commit adds a new Kconfig option CLOCK_CONTROL_NPCX_EXTERNAL_SRC.
With this option enabled, the internal 32.768 KHz clock (LFCLK) is
generated by the on-chip Crystal Oscillator (XTOSC). Otherwise, the
LFCLK is generated by the Low-Frequency Clock Generator (LFCG).
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
NPCX power.c use LOG_MODULE_DECLARE(soc), but NPCX chip doesn't
register soc log module. This CL register soc log in soc.c to fix NPCX
build error for power management & log system.
Signed-off-by: Wealian Liao <WHLIAO@nuvoton.com>
Configures Segger RTT and SystemView data linker sections to DTCM by
default on i.MX RT SoCs if there is a zephyr,dtcm chosen node in
devicetree. This fixes a build warning in
samples/subsys/shell/shell_module for the mimxrt1170_evk_cm7 and
mimxrt1170_evk_cm4 platforms, which don't currently have a zephyr,dtcm
chosen node.
Note that there are runtime issues with Segger RTT and SystemView on
this board that need further debug, but submitting this patch now to
address nightly CI failures.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
This adds power management support for the STM32WL series.
Suspend-to-idle is mapped to the three stop states (wake up from any
EXTI, including LPTIM), and soft-off can trigger either standby or
shutdown (wake up in reset).
Signed-off-by: Fabio Baltieri <fabio.baltieri@gmail.com>
The PS/2 module in npcx provides a hardware accelerator mechanism
including an 8-bit shift register, a state machine, and control logic
that handle both the incoming and outgoing data. The hardware
accelerator mechanism is shared by 4 PS/2 channels. To support it,
this CL separates the PS/2 driver into channel and controller drivers.
The controller driver is in charge of the PS/2 transaction. The channel
driver is in charge of the connection between the Zehpyr PS/2 API
interface and controller driver.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
This commit adds the asserts symbol in Kconfig to enable/disable
asserts functionality for stm32 series. These would be used in
stm32cube hal & ll drivers.
Signed-off-by: Krishna Mohan Dani <krishnamohan.d@hcl.com>
This is a work in progress initial submission for the
Microchip MEC172x family SoC. This submission does
not contain all header files or power management.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
1. Added RT10xx and RT11xx configs
2. Added a new soc file for rt117x. There are clock differences
between the RT10xx and RT11xx series, hence the soc files
have been separated.
Signed-off-by: Ryan QIAN <jianghao.qian@nxp.com>
Enable Instruction Cache
Warning: no flash driver yet available for STM32l5
But cache coherency management (cache invalidate)
will be rerquired when implementing flash driver.
ICAHE must be disabled for any flash write opeartion.
Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
Enable Instruction cache accelerator for Cortex M4
first 1MB of Flash.
As per Reference Manual: no need for cache coherency management
Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
Convert the various device_get_binding() calls used to get the device
clock node to use DEVICE_DT_GET. The latter is processed at link time,
so it should be a bit more efficient.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Add power management support to STM32L0 series.
The SoC have a single stop state that can be used with LPTIM as a system
timer, as well as a standby mode where the system resets on exit.
Signed-off-by: Fabio Baltieri <fabio.baltieri@gmail.com>
NPCX WIMU CR_SIN is used to wake up soc from NPCX sleep power state.
The wake-up IRQ enabled when UART init. It causes the wake-up IRQ to
generate many extra interrupt events, which causes the system too busy
to handle other events. This PR moves the UART wake-up IRQ enabling
from UART init to npcx_power_enter_system_sleep() to avoid the
interrupt storm.
Signed-off-by: Wealian Liao <WHLIAO@nuvoton.com>
Set the defalut value of SYS_CLOCK_HW_CYCLES_PER_SEC Kconfig option
from the Device Tree. The `clock-frequency` property of the DT cpu@0
node is a single source of truth defining the CPU frequency. This is
the value used e.g. by all Atmel drivers.
For Atmel SAM family CPU clock is currently the only supported system
clock source. Ensure that kernel understanding of the hardware clock
frequency is the correct one.
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
MPS2 AN521 is a dual (Cortex-M33) core where the two cores
have different capabilities. E.g CPU0 implements TrustZone-M,
while CPU1 implements the FPU. Therefore we introcude separate
Kconfig symbols for the two SoC variants, and use these to
select the different Cortex-M capabilities. We also update
the definitions of __MPU/FPU/SAU/DSP variant in soc.h to make
them get the value from the Kconfig settings, directly.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This CL introduces six properties, clock-frequency, core-prescaler,
apb1/2/3/4-prescaler in pcc (Power and Clock Controller) node to
configure clock settings. It also removed the original Kconfig options
used for the same purpose.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Rename OSC_CLK as OFMCLK to meet npcx datasheet. The Oscillator
Frequency Multiplier Clock (OFMCLK), which is derived from
High-Frequency Clock Generator (HFCG), is the source clock of cortex-m4
core and most of NPCX hardware modules.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
We should gurantee that we do not use SRAM during Zephyr early
boot, until SystemInit has returned. This commit aims to ensure
that SystemInit will be branched to, without first pushing args
to stack, even when no optimizations are selected. We chose to
define z_platform_init in assembly directly (instead of using
inline assembly) as it appears to be a cleaner design.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Use a common implementation for z_platform_init
in nRF SoC family. The implementations are
identical, so no need to maintain separate
identical versions of them. The commit does not
introduce behavioral changes.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Wealian Liao