Commit Graph

3 Commits

Author SHA1 Message Date
Anas Nashif 0a38ce0395 boards: xt-sim: make board depend on SIMULATOR_XTENSA
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-09-11 16:29:55 -04:00
Leandro Pereira 27ea2d8eb7 arch: xtensa: Convert Xtensa port to use gen_isr_table
The Xtensa port was the only one remaining to be converted to the new
way of connecting interrupts in Zephyr.  Some things are still
unconverted, mainly the exception table, and this will be performed
another time.

Of note: _irq_priority_set() isn't called on _ARCH_IRQ_CONNECT(), since
IRQs can't change priority on Xtensa: while the architecture has the
concept of interrupt priority levels, each line has a fixed level and
can't be changed.

Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
2017-08-09 12:26:14 -07:00
Andrew Boie 4f69bdaa0d sanitycheck: build more Xtensa SOCs
Now that we can specify what toolchain is intended for each
SOC, enable some more SOCs to be built.

A full sanitycheck run will require the installation of both
RF-2016.4 and RG-2016.4 releases.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-05-18 07:18:36 -04:00