Commit Graph

102 Commits

Author SHA1 Message Date
Kumar Gala c55de26597 boards: riscv: Remove unneeded zephyr_include_directories
The include of ${ZEPHYR_BASE}/drivers isn't needed anymore for
board code so remove it.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2021-03-23 16:44:32 -05:00
Anas Nashif 35910040f1 boards: it8xxx2_evb: set architecture correctly
riscv -> riscv32

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2021-03-04 07:14:11 -06:00
Kumar Gala ff5b040f78 boards: Add i2s to supported list for testing
Add i2s as a supported feature on at least one board for each driver
that we have in tree to get CI coverage.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2021-02-26 14:21:59 -06:00
Anas Nashif ff24090527 tests: filter default platforms
Do not attempt to build/run all tests. Emulation platforms should
primarily build kernel and architecture related tests.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2021-02-19 14:41:01 -05:00
Kumar Gala c54005235c riscv: ite: it8xxx2: Rework device_get_binding for pinmux
Switch to use DEVICE_DT_GET instead of device_get_binding for pinmux
device.  As part of this change drop the "label" property from
the pinmux devicetree node and update the binding and dts files to
reflect that.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2021-02-16 09:45:57 -05:00
Kumar Gala f6b7dd09ec pinmux: sifive: Convert SiFive pinmux to be devicetree based
Add a simple pinctrl node for the IOF registers under the GPIO
controller node to be used by the pinmux driver.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2021-02-15 08:33:00 -05:00
Kumar Gala d6b4995d6a riscv: rv32m1: Rework device_get_binding for pinmux
Switch to use DEVICE_DT_GET instead of device_get_binding for pinmux
device.  As part of this change drop the "label" property from
the pinmux devicetree node and update the binding and dts files to
reflect that.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2021-02-15 08:32:41 -05:00
Adam Jeliński 86ca5ff562 m2gl025_miv: Adjust frequencies and performance
The default frequency for this board in Renode is 66 MHz. This needs to
be even with `SYS_CLOCK_HW_CYCLES_PER_SEC` to avoid such problems as in
the #31726 issue.

Unfortunately, the difference in these values was helpful for some tests
that are failing with 66 MHz set in both places. It created artificial
boost in certain circumstances.

The frequencies in the default Renode platform description (`.repl`)
file for MI-V were overridden with 4 MHz value that seems to be better
tolerated based on testing. The `SYS_CLOCK_HW_CYCLES_PER_SEC` was
adjusted as well.

To solve the rest of the issues, `cpu PerformanceInMips` was set to 4.
It seems tests are completed faster with such a value.

This commit fixes #31726.

Signed-off-by: Adam Jeliński <ajelinski@antmicro.com>
2021-02-09 19:41:27 -05:00
Peter Bigot 092758cda6 boards: hifive1: remove incorrect alias for GPIO use of LEDs
The devicetree only provides PWM-compatible LEDs.  Remove the aliases
that suggest it supports GPIO-compatible LEDs.

Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
2021-02-02 17:58:23 -05:00
Anas Nashif c31ce55c58 timer: TICKLESS_CAPABLE is now without prompt
TICKLESS_CAPABLE is now selectable only and without prompt, so remove it
from _defconfig files and select it directly by the timer.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2021-01-21 22:51:19 -05:00
Martin Åberg a362463fdf boards: qemu_riscv64 use virt machine
Upgrade board specification to use the VirtIO board.

Keeps FPU run-time support disabled since the RISC-V 64-bit FPU
support in kernel appears to be non-functional.

Signed-off-by: Martin Åberg <martin.aberg@gaisler.com>
2021-01-15 13:06:33 -05:00
Martin Åberg 8a2d5aa716 boards: qemu_riscv32 use virt machine
Upgrade board specification to use the VirtIO board.

Signed-off-by: Martin Åberg <martin.aberg@gaisler.com>
2021-01-15 13:06:33 -05:00
Martin Åberg d2e9568543 riscv: make COMPRESSED_ISA independent of FLOAT_HARD
The CONFIG_FLOAT_HARD config previously enabled the C (compressed)
ISA extensions (CONFIG_COMPRESSED_ISA). This commit removes that
dependency.

Signed-off-by: Martin Åberg <martin.aberg@gaisler.com>
2021-01-15 13:06:33 -05:00
Tim Lin 981166eb8e drivers/i2c: add i2c driver on it8xxx2 platform
This commit is about the it8xxx2 i2c master driver which
includes six SMBus channels. The enhanced channel i2c3,
i2c4, i2c5 are controller which are designed to support
the I2C protocol.

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
2021-01-15 11:22:57 -05:00
Katsuhiro Suzuki bbc563f5ac boards/dts: riscv: add SiFive FE310 watchdog driver bindings
This patch adds watchdog driver bindings and enable it for SiFive
HiFive1 rev.B board.

Signed-off-by: Katsuhiro Suzuki <katsuhiro@katsuster.net>
2021-01-15 07:19:38 -06:00
Andy Ross e956639dd6 kernel: Remove CONFIG_LEGACY_TIMEOUT_API
This was a fallback for an API change several versions ago.  It's time
for it to go.

Fixes: #30893

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2021-01-14 21:33:16 -05:00
Peter Bigot e017441ca0 boards: remove has-be32k from SPI NOR mtd nodes
Use of this property has no effect since it was by SFDP erase data in
Zephyr 2.4.

Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
2021-01-13 11:58:37 -06:00
Robert Winkler b18309c0d7 boards: doc: Add information about generating litex_vexriscv SoC
This commit adds more information about the litex_vexrscv board
target, including references to related projects and instruction
about generating bitstream for the Digilent Arty A7-35T Board.

Signed-off-by: Robert Winkler <rwinkler@antmicro.com>
2020-12-16 12:49:16 -05:00
Cheryl Su 968dd2107b boards/riscv: add new riscv platform-it8xxx2
We create a new platform for our chip series it8xxx2.
It is a riscv base soc.

Signed-off-by: Cheryl Su <cheryl.su@ite.com.tw>
2020-12-16 08:47:36 -05:00
Pawel Czarnecki 967d336dae boards: riscv: litex_vexriscv: enable clock control driver
This enables the LiteX clock control driver for litex_vexriscv platform.

Signed-off-by: Pawel Czarnecki <pczarnecki@internships.antmicro.com>
Signed-off-by: Mateusz Holenko <mholenko@antmicro.com>
2020-12-06 12:35:16 -05:00
Pawel Czarnecki 98fd9d0975 boards/dts: riscv: litex_vexriscv: add clock control driver to devicetree
This extends litex_vexriscv.dts file by adding clock controller nodes.

Signed-off-by: Pawel Czarnecki <pczarnecki@internships.antmicro.com>
Signed-off-by: Mateusz Holenko <mholenko@antmicro.com>
2020-12-06 12:35:16 -05:00
Alexandre Mergnat e76b8e427d boards: hifive1_revb: add support for memory protection features
Add this board to E31 core family.

Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com>
2020-11-09 15:37:11 -05:00
Tomasz Bursztyka e18fcbba5a device: Const-ify all device driver instance pointers
Now that device_api attribute is unmodified at runtime, as well as all
the other attributes, it is possible to switch all device driver
instance to be constant.

A coccinelle rule is used for this:

@r_const_dev_1
  disable optional_qualifier
@
@@
-struct device *
+const struct device *

@r_const_dev_2
 disable optional_qualifier
@
@@
-struct device * const
+const struct device *

Fixes #27399

Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2020-09-02 13:48:13 +02:00
Pawel Sagan cc30fb871b drivers: i2s: Add LiteX I2S controller driver
This introduces LiteX I2S driver supporting the following features:
    - 8,16,24,32 bit sample width,
    - mono/stereo sound,
    - different sample frequencies
    - big/little-endian data format,
    - concatenated channels mode (for selected sample widths only),
    - slave/master mode operation.

Signed-off-by: Pawel Sagan <psagan@internships.antmicro.com>
Signed-off-by: Mateusz Holenko <mholenko@antmicro.com>
2020-08-26 08:17:42 -04:00
Anas Nashif ce59510127 arch: xip: cleanup XIP Kconfig
unify how XIP is configured across architectures. Use imply instead of
setting defaults per architecture and imply XIP on riscv arch and remove
XIP configuration from individual defconfig files to match other
architectures.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2020-08-07 09:50:22 -04:00
Kumar Gala 38cd37f726 dts: remove incorrect use of mmio-sram compatible
For memory that is truly device_type = "memory" we should not have a
mmio-sram compatible.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-07-28 07:31:01 -05:00
Peter Bigot 9dc7640ede spi-device: set CS gpio flags for all devices that had none
The generic SPI GPIO chip select support now respects devicetree flags
for signal active level.  Update all cs-gpios properties to specify
active low.

Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
2020-07-09 06:07:07 -05:00
Andrew Boie a9670ab5cf boards: centralize QEMU icount management
Instead of endlessly repeating the same command line args,
centralize this and tune the shift value on a per-board
basis.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2020-06-24 20:28:36 -04:00
Maureen Helm cec9735d8a boards: riscv: Conditionalize pinmuxes on rv32m1_vega board
Conditionalizes pinmuxes on associated driver configs (CONFIG_SERIAL,
CONFIG_I2C, etc.) for the rv32m1_vega board to avoid possible conflicts
between peripherals.

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2020-05-22 14:51:07 +02:00
Kumar Gala 3393600017 boards: Make GPIO pin config default for LEDs instead of PWM
Add an additional check for CONFIG_PWM to decide if pins associated with
LED are configured for GPIO or PWM.

Fixes #25337

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-05-20 10:32:11 +02:00
Wentong Wu bb80d3528e boards: hifive1: enable icount mode
Enable icount mode for hifive1 platform, The icount shift value is
selectd based on cpu clock frequency of this platform. The virtual
cpu will execute one instruction every 2^shift ns of virtual time.

Signed-off-by: Wentong Wu <wentong.wu@intel.com>
2020-05-14 13:52:07 +02:00
Wentong Wu 49bf0ff1ff boards: qemu_riscv64: enable icount mode
Enable icount mode for qemu_riscv64 platform, The icount shift value
is selectd based on cpu clock frequency of this platform. The virtual
cpu will execute one instruction every 2^shift ns of virtual time.

Signed-off-by: Wentong Wu <wentong.wu@intel.com>
2020-05-14 13:52:07 +02:00
Wentong Wu 589a0c22ff boards: qemu_riscv32: enable icount mode
Enable icount mode for qemu_riscv32 platform, The icount shift value
is selectd based on cpu clock frequency of this platform. The virtual
cpu will execute one instruction every 2^shift ns of virtual time.

Signed-off-by: Wentong Wu <wentong.wu@intel.com>
2020-05-14 13:52:07 +02:00
Martí Bolívar 6e8775ff84 devicetree: remove DT_HAS_NODE_STATUS_OKAY
Several reviewers agreed that DT_HAS_NODE_STATUS_OKAY(...) was an
undesirable API for the following reasons:

- it's inconsistent with the rest of the DT_NODE_HAS_FOO names
- DT_NODE_HAS_FOO_BAR_BAZ(node) was agreed upon as a shorthand
  for macros which are equivalent to
  DT_NODE_HAS_FOO(node) && DT_NODE_HAS_BAR(node) &&
- DT_NODE_HAS_BAZ(node), and DT_HAS_NODE_STATUS_OKAY is an odd duck
- DT_NODE_HAS_STATUS(..., okay) was viewed as more readable anyway
- it is seen as a somewhat aesthetically challenged name

Replace all users with DT_NODE_HAS_STATUS(..., okay), which is
semantically equivalent.

This is mostly done with sed, but a few remaining cases were done by
hand, along with whitespace, docs, and comment changes. These special
cases include the Nordic SOC static assert files.

Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
2020-05-13 18:24:42 +02:00
Kumar Gala fdd85d5ad7 dts: Rename DT_HAS_NODE macro to DT_HAS_NODE_STATUS_OKAY
Rename DT_HAS_NODE to DT_HAS_NODE_STATUS_OKAY so the semantics are
clear.  As going forward DT_HAS_NODE will report if a NODE exists
regardless of its status.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-05-06 05:25:41 -05:00
Peter Bigot 113c814517 boards: riscv: rv32m1_vega: fix parse error in pinmux
If processed this would have produced a syntax error.

Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
2020-05-05 13:40:55 -05:00
Kumar Gala 98e5123593 boards: arm: rv32m1_vega: Replace old DT macros with new ones
Replace DT_ALIAS_GPIO_x_LABEL with DT_NODELABEL references to get the
device name for the gpio ports.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-04-23 15:50:26 -05:00
Corey Wharton d873573f76 tests: fp_sharing: Enable build-only tests for RISC-V QEMU platform
Enables build-only tests for the qemu_riscv32 platform.

Signed-off-by: Corey Wharton <coreyw7@fb.com>
2020-04-22 16:39:48 -07:00
Jeanina Dragusin 40ee38a945 bluetooth: controller: enable privacy for RV32M1
This patch adds the selection of the necessary CONFIG_*
options for allowing the use of privacy on VEGA platform

Signed-off-by: Jeanina Dragusin <ancajeanina.dragusin@nxp.com>
2020-04-15 13:43:00 -05:00
Jeanina Dragusin 6099e0f928 bluetooth: controller: openisa/RV32M1: add RPA support
The radio on the VEGA platform will now be able to resolve Resolvable
Private Addresses through the use of the CAUv3 hardware. With this
patch the RPA feature is now fully supported on the Controller:
RPA addresses are generated with local IRK and resolved with
previously exchanged peer IRK.

Signed-off-by: Jeanina Dragusin <ancajeanina.dragusin@nxp.com>
2020-04-15 13:43:00 -05:00
Kumar Gala f928e1b144 drivers: gpio: rv32m1: Convert driver to new DT_INST macros
Convert driver to use DT_INST macros and remove related board per
instance Kconfig symbol usage.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-04-10 14:38:04 -05:00
Kumar Gala 019d611031 boards: riscv: rv32m1_vega: remove stale Kconfig PWM setting
Per instance Kconfig symbols aren't used by the rv32m1 lpspi driver
so remove the unnecessary setting of PWM_2.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-04-10 14:38:04 -05:00
Kumar Gala 8f0018663f drivers: pinmux: rv32m1: Convert driver to new DT_INST macros
Convert driver to use DT_INST macros and remove related board per
instance Kconfig symbol usage.

Updated the openisa,rv32m1_vega-pinmux binding to require the label
property and updated the rv32m1.dtsi to add label properties for the
pinmux nodes.

Also update gpio_basic_api test to use DT_NODELABEL.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-04-10 14:38:04 -05:00
Kumar Gala 8c60bc0b07 drivers: spi: rv32m1_spi: Convert driver to new DT_INST macros
Convert driver to use DT_INST macros and remove related board per
instance Kconfig symbol usage.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-04-10 14:38:04 -05:00
Kumar Gala 03d48d894d drivers: serial: rv32m1_lpuart: Convert driver to new DT_INST macros
Convert driver to use DT_INST macros and remove related board per
instance Kconfig symbol usage.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-04-10 14:38:04 -05:00
Kumar Gala 376c5a4e4f drivers: i2c: i2c_rv32m1_lpi2c: Convert driver to new DT_INST macros
Convert driver to use DT_INST macros and remove related board per
instance Kconfig symbol usage.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-04-10 14:38:04 -05:00
Kumar Gala 8c78fa85ad boards: riscv: rv32m1_vega: Convert from Kconfig to DT_NODELABEL
As prep for drivers being converted to utilize DT_INST and removal of
per instance Kconfig symbols, move board pinmux.c code to utilize
DT_NODELABEL instead.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-04-10 14:38:04 -05:00
Kumar Gala b263a3379c soc: riscv: openisa_rv32m1: Convert from Kconfig to DT_NODELABEL
As prep for drivers being converted to utilize DT_INST and removal of
per instance Kconfig symbols, move soc.c code to utilize DT_NODELABEL
instead.

Also rename various node labels to match the SoC docs.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-04-10 14:38:04 -05:00
Anas Nashif 2215d21104 doc: fix broken links in README and board docs
Point to zephyr/sdk release pages instead of non-existent downloads page
on project website.

Fixes #21706

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2020-03-12 17:18:49 -04:00
George Stefan 350dc0601d boards: riscv: rv32m1_vega: remove no power-save limitation
Now the VEGABoard BLE supports power-saving,
so the docs need to be updated accordingly.

Signed-off-by: George Stefan <george.stefan@nxp.com>
2020-03-12 17:05:02 +02:00