Provide more docs on ngpios and try and clarify the case if there are
holes in the GPIO slot range how ngpios should work.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
In npcx7 series, there're 8 Pulse Width Modulator (PWM) modules and each
one support generating a single 16-bit PWM output. A 16-bit clock
prescaler (PRSCn) and a 16-bit counter (CTRn) determine the cycle time,
the minimal possible pulse width, and the duty-cycle steps.
Beside introducing pwm driver for Nuvoton NPCX series, this CL also
includes:
1. Add PWM device tree declarations.
2. Zephyr PWM api implementation.
3. Add aliases in npcx7m6fb_evb board device tree file for supporting
samples/basic/blinky_pwm application and pwm test suites
Signed-off-by: Mulin Chao <MLChao@nuvoton.com>
Add an emulation controller which routes SPI traffic to an attached
emulator. Only one emulator is supported per bus at present, since
chip-selction functionality is not present.
This allows drivers for SPI peripherals to be tested on systems that
don't have that peripheral attached, with the emulator handling the SPI
traffic.
Signed-off-by: Simon Glass <sjg@chromium.org>
Only difference compared to existing Xe variant is less flash memory.
Existing nodes for DAC were moved up one level to stm32g474.dtsi
Signed-off-by: Martin Jäger <martin@libre.solar>
In case a "required: False" enum binding doesn't mention a
default value, but a default value makes sense to be set in the code,
DT_ENUM_IDX_OR could be used to provide the default idx to be used.
New macro comes with appropriate tests.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Reused Linux bindings were using /* */ in some property description
fields.
This is not compatible with legacy device tree api which expands
these fields in commented sections of generated file
devicetree_legacy_unfixed.h resulting in compilation issue.
Seen when running tests/lib/devicetree/legacy_api.
Remove /* */ for now, waiting legacy api to be removed.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Generalize io-channels and io-channel-names devicetree node properties
and move their definitions to base.yaml. Keep binding specific
description where relevant.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Change default pinmux of functional pads to GPIOs. It includes:
1. PIN96.A0.A2.A4 - If internal flash is supported
2. PIND2.00 - Default PSL inputs
3. PIN31.30.27.26.25.24.23.22 - Keyboard inputs
4. PIN21.20.17.16.15.14.13.12.11.10.07.06.05.04.82.83.03.B1 - Keyboard
outputs
5. Add description for soc_pinctrl_mux_configure() usage.
It also fixed the typo and inverse mistakes in npcx7-alts-map.dtsi.
Signed-off-by: Mulin Chao <MLChao@nuvoton.com>
This change allows to use SSD1306 based displays to be used on the
SPI bus as well.
Adding SPI shield.
Tested on SSD1306 and SSD1309 based displays using I2C.
Tested on SSD1309 based display using SPI.
Signed-off-by: Marco Peter <marco@peter-net.ch>
This CL adds more comments for each macro functions used for device tree
file for better explanations. It also changes all hex values in soc.c to
lower case.
Signed-off-by: Mulin Chao <MLChao@nuvoton.com>
This CL contains the drivers of NPCX Host Sub-Modules that serve as an
interface between the Host and Core domains. For most of them, the Host
can configure these modules via eSPI(Peripheral Channel)/LPC by
accessing 'Configuration and Control register Set' which IO base address
is 0x4E as default. And the interrupts in core domain help handling any
events from host side.
In this commit, we introduced six host sub-modules. It includes:
1. Keyboard and Mouse Controller (KBC) interface.
2. Power Management (PM) channels.
3. Shared Memory mechanism (SHM).
4. Core Access to Host Modules (C2H).
5. Mobile System Wake-Up functions (MSWC).
6. Serial Port (Legacy UART)
The tasks in application layer such as 8042, ACPI and host command can
cooperation with this driver by connecting api or callback functions.
Signed-off-by: Mulin Chao <MLChao@nuvoton.com>
In npcx7 series, all of them support the Intel Enhanced Serial
Peripheral Interface (eSPI) Revision 1.0. This specification provides a
path for migrating host sub-devices via LPC to a lower pin count, higher
bandwidth bus. In addition to Host communication via the peripheral
channel, it provides virtual wires support, out-of-band communication,
and device mastering option over the Chipset SPI flash.
Becisdes introducing eSPI device in npcx7, this CL also includes:
1. Add eSPI device tree declarations.
2. Add npcx7-espi-vws-map.dtsi to present the relationship between eSPI
Virtual-Wire signals, eSPI registers, and wake-up input sources.
3. Zephyr eSPI api implementation.
4, Add OOB (Out of Band tunneled SMBus) support.
5. Add configuration files for eSPI test suites.
Signed-off-by: Mulin Chao <MLChao@nuvoton.com>
stm32f1 series pin controller IP is not compatible with other stm32
series.
Set the dedicated st,stm32f1-pinctrl compatible for pinctrl node.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Provide yaml bindings for st,stm32f1-pinctrl copmpatible.
It differs from generic stm32 pinctrl bindings on the following points:
- Pinmux "function" parameter: Alternate, General output, Input, Analog
- Pinmux supports an additional "remap" parameter to encode potential
remapping configuration
- Bias configs only apply to input modes
- Drive and speed configs only apply to output modes
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Rename compatible st,stm32-pinmux to st,stm32-pinctrl to better
reflect the nature of upcoming child nodes.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
STM32L151xC SoC differs from other L1 SoCs in RAM (32KiB) and
flash (256KiB) size, and amount of interrupts (57, see STM32Cube).
Devicetree and Kconfig support.
Signed-off-by: Noelle Clement <noelleclement@hotmail.com>
Allow to reconfigure UART baudrate on ESP and on host MCU, so a
non-default baudrate can be used for communication. This option helps
for example to increase network bandwidth without touching ESP chip
firmware.
Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
Move pixel format setting (RGB565/RGB888) to DeviceTree. Add support for
changing pixel format at runtime.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Adds imx rt support.
Allows n-number of can interfaces based on device-tree.
Adds a "common" irq name.
Added CAN bus pins and dts for 1060 and 1064 EVK.
Signed-off-by: Rick Talbott <rtalbott@fastmail.com>
* Add ADC2 and ADC3 to the F103xE definition.
* Add a dtsi file for the F103xG based on the F103xE.
The F103xG has 1 MB of flash, 96 KB of RAM, and additional timers
TIM9/10/11/12/13/14.
Signed-off-by: Paul Fagerburg <pfagerburg@google.com>
Move the devicetree bindings for Analog-to-Digital Converters (ADCs)
from dts/bindings/iio/adc to dts/bindings/adc as Zephyr does not have
an IIO layer.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
update rt6xx series sram mapping to skip 0x180000,
reserved for DSP usage.
this fixes tests/subsys/debug/coredump for this board
Signed-off-by: Hake Huang <hake.huang@oss.nxp.com>
The sam4l pinctrl contains two entries with wrong values. Fix the
typo to create valid pinctrl map.
Fixes#28538.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
HAS_DTS_I2C is now selected by I2C and
always used as I2C && HAS_DTS_I2C.
It could then be purely removed.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Change #28199 introduced systick configuration from device tree.
For now this should not be used on platforms that support alternate
tick source, as this is the case on l4 and wb series with LPTIM.
Until dts allows to configure lptim from dts, keep systick disabled
by default on these platforms.
Fixes#28280
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Use setting from devicetree to drive the default setting for
CORTEX_M_SYSTICK. We update the dts files to default systick to be
enabled since the major of cortex-m platforms utilize it by default
(except on Nordic SoCs, TI CC13x2/CC26x2 and MEC1501 in which we
default to disabled).
Fixes#25299
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
The host command peripheral device API abstracts how an embedded
controller sends and receives data from a host on a bus. Each bus like
eSPI, SPI, or I2C would implement their own host command peripheral
device. Each hardware device would then handle the necessary hardware
access to send and receive data over that bus.
The chosen host command peripheral device will be used by the host
command handler framework to send and receive host data correctly.
Signed-off-by: Jett Rink <jettrink@google.com>