Commit Graph

11 Commits

Author SHA1 Message Date
Mazen NEIFER f7538f0005 Xtensa port: Added support in arch/cpu.h for Xtensa cores.
Change-Id: If4a053f6164fd2fa30f148e6e907f662cda50722
Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
2017-02-13 08:04:27 -08:00
David B. Kinder ac74d8b652 license: Replace Apache boilerplate with SPDX tag
Replace the existing Apache 2.0 boilerplate header with an SPDX tag
throughout the zephyr code tree. This patch was generated via a
script run over the master branch.

Also updated doc/porting/application.rst that had a dependency on
line numbers in a literal include.

Manually updated subsys/logging/sys_log.c that had a malformed
header in the original file.  Also cleanup several cases that already
had a SPDX tag and we either got a duplicate or missed updating.

Jira: ZEP-1457

Change-Id: I6131a1d4ee0e58f5b938300c2d2fc77d2e69572c
Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-01-19 03:50:58 +00:00
Jean-Paul Etienne cd83e85edc arch: added support for the riscv32 architecture
RISC-V is an open-source instruction set architecture.
Added support for the 32bit version of RISC-V to Zephyr.

1) exceptions/interrupts/faults are handled at the architecture
   level via the __irq_wrapper handler. Context saving/restoring
   of registers can be handled at both architecture and SOC levels.
   If SOC-specific registers need to be saved, SOC level needs to
   provide __soc_save_context and __soc_restore_context functions
   that shall be accounted by the architecture level, when
   corresponding config variable RISCV_SOC_CONTEXT_SAVE is set.

2) As RISC-V architecture does not provide a clear ISA specification
   about interrupt handling, each RISC-V SOC handles it in its own
   way. Hence, at the architecture level, the __irq_wrapper handler
   expects the following functions to be provided by the SOC level:
   __soc_is_irq: to check if the exception is the result of an
                 interrupt or not.
   __soc_handle_irq: handle pending IRQ at SOC level (ex: clear
                     pending IRQ in SOC-specific IRQ register)

3) Thread/task scheduling, as well as IRQ offloading are handled via
   the RISC-V system call ("ecall"), which is also handled via the
   __irq_wrapper handler. The _Swap asm function just calls "ecall"
   to generate an exception.

4) As there is no conventional way of handling CPU power save in
   RISC-V, the default nano_cpu_idle and nano_cpu_atomic_idle
   functions just unlock interrupts and return to the caller, without
   issuing any CPU power saving instruction. Nonetheless, to allow
   SOC-level to implement proper CPU power save, nano_cpu_idle and
   nano_cpu_atomic_idle functions are defined as __weak
   at the architecture level.

Change-Id: I980a161d0009f3f404ad22b226a6229fbb492389
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
2017-01-13 19:52:23 +00:00
Andrew Boie 9433895954 nios2: basic build, non-functional
Basic build framework for Nios2. Everything is stubbed out,
we just want to have a build going so that we can start to
parallelize implementation tasks.

This patch is not intended to be functional, but should be
able to produce a binary for all the nanokernel-based
sanity checks.

Change-Id: I12dd8ca4a2273f7662bee46175822c9bbd99202a
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-05-03 23:18:45 +00:00
Anas Nashif 77ba3c3b8b kconfig: define architecture as a kconfig variable
Do not depend on environment variables and use a kconfig variable
for defining the architecture.

In addition, remove the X86_32 variable, it just duplicates X86 for
not good reason, at least until start supporting MCUs with 64bit.

Change-Id: Ia001db81ed007e6a43f34506fed9be1345b88a4b
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:24:52 -05:00
Javier B Perez Hernandez f7fffae8aa Change BSD-3 licenses to Apache 2
Change all the Intel and Wind River code license from BSD-3 to Apache 2.

Change-Id: Id8be2c1c161a06ea8a0b9f38e17660e11dbb384b
Signed-off-by: Javier B Perez Hernandez <javier.b.perez.hernandez@linux.intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Signed-off-by: Allan Stephens <allan.stephens@windriver.com>
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-02-05 20:24:29 -05:00
Anas Nashif 54ac4484d7 Rename VXMICRO_ARCH and VXMICRO
Change-Id: I6f3858de98333ec466aa876c5f2887faa8e276e2
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:14:16 -05:00
Anas Nashif f2520f87a2 Rename VXMICRO_ARCH_arc -> CONFIG_ARC
Change-Id: I4aca181523f50f43ee01e1be0c20a9ad844ef618
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:14:16 -05:00
Anas Nashif 274622ea69 Rename VXMICRO_ARCH_arm -> CONFIG_ARM
Change-Id: I32b2e39781825504e7936b3df0c864988650c35c
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:14:16 -05:00
Anas Nashif 191fc279ce Rename VXMICRO_ARCH_x86 -> CONFIG_X86_32
Change-Id: Ie1bcfebce1db838ea994cb3626396ea032225830
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2016-02-05 20:14:16 -05:00
Dan Kalowsky c02dd34277 Renaming include/nanokernel to include/arch
Renaming the directory include/nanokernel to be include/arch, which
better reflects the real nature of the directory and the contents
inside.

Change-Id: I2bc33ebc6715e2f0403227a558279fdf52398ade
Signed-off-by: Dan Kalowsky <daniel.kalowsky@intel.com>
2016-02-05 20:14:12 -05:00