OrgZephyr/zephyr
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6 Commits

Author SHA1 Message Date
Boon Khai Ng 69eb4c6c8a boards: arm64: intel_socfpga_agilex: Enable QSPI at agilex board 
This patch is to enable QSPI at Intel SoC FPGA Agilex Board

Signed-off-by: Boon Khai Ng <boon.khai.ng@intel.com>
 2022-09-01 14:30:59 -04:00
Kumar Gala 10329165be serial: remove defconfig/proj setting of serial drivers 
Now that serial drivers are enabled based on devicetree we can remove
any cases of them getting enabled by *defconfig and proj.conf files.

Signed-off-by: Kumar Gala <galak@kernel.org>
 2022-07-26 09:29:24 -05:00
Maureen Helm 267bba62d3 dts: arm64: intel: Move SoC devicetree includes under a vendor directory 
Cleans up SoC devicetree include file locations to follow the convention
of dts/<arch>/<vendor>/

Signed-off-by: Maureen Helm <maureen.helm@intel.com>
 2022-05-09 17:54:48 -04:00
Nazar Kazakov 9713f0d47c everywhere: fix typos 
Fix a lot of typos

Signed-off-by: Nazar Kazakov <nazar.kazakov.work@gmail.com>
 2022-03-14 20:22:24 -04:00
Erwan Gouriou 7c25fd3c2e boards: doc: Clarify a generic statement 
This sentence ("Other hardware features are not supported by the
Zephyr kernel."), which could be found in a high number of boards
documentation, is misleading on two levels:
- peripheral support is not a kernel business
- in most of cases, features are actually supported but not enabled.

Fix this.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
 2022-01-11 11:54:22 +01:00
Siew Chin Lim a71d6f2c0c boards: arm64: Build Zephyr for Intel SoC FPGA Agilex development kit 
This is the initial Zephyr support for Intel SoC FPGA Agilex support.
Agilex has quad-core 64-bit Arm Cortex*-A53.

This patch build Zephyr for Agilex development kit with 256KB SDRAM and
support hello_world sample code. The Zephyr will need to be loaded by
Intel Arm Trusted Firmware (ATF).

Agilex Zephyr boot flow:
	FSBL:ATF BL2(EL3) -> SSBL:ATF BL31(EL3) -> OS:Zephyr(EL2->EL1)

Intel ATF can be loaded from:
	https://github.com/altera-opensource/arm-trusted-firmware.git

Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
 2021-10-12 08:37:03 -04:00