The OpenISA RV32M1 pinctrl groups need a dummy pinctrl node to populate
with pinctrl options at the board level.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
This adds the CMOS RTC node to the common devicetree files
for x86. Note that this is not added to Lakemont, as it is
usually used for embedded applications which would not have
CMOS RTC.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Add DTS binding for Motorola MC146818 compatible Real Time Clock.
This is being used for the RTC/CMOS timer on x86 PC-compatible
platforms.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
cavs15 uses different base addresses for IP blocks than the rest
and thus needs its own configuration in device tree.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
Add optional PINCTRL support to the Microchip XEC PS2 driver
shared between MEC15xx and MEC172x families.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Update the Microchip XEC PS2 driver to support MEC172x.
NOTE: MEC15xx has two PS2 controllers and
MEC172x has one.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Comparator will monitor signal though ADC channel, based on
user configuration, callback will be triggered.
This will enable comparator functionality for nuvoton MCU utilizing its
ADC threshold detection feature. Implementation is exported through
sensor trigger API. Use of CONFIG_ADC_CMP_NPCX is required.
Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
add pin control nodes for LPC SOCs, to be filled with pin control
settings at the board level.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
In the EC application, the system may jump between two built Zephyr
images when necessary. When jumping from the current image to the other,
the firmware switches the eSPI-related pins to GPIO function at
initialization if define alt1_no_lpc_espi in def-io-conf-list.
It causes the eSPI to reset and breaks the eSPI communication after the
image jump. This patch prevents it by removing alt1_no_lpc_espi from
def-io-conf-list.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
The LPC platforms define memory in SRAM blocks that can be
combined to represent larger memory blocks to the CPU. Change
the cpu0 allocation to use SRAM0-SRAM2 for 192K and change
cpu1 to use SRAM3-SRAM4 for 80K.
Signed-off-by: David Leach <david.leach@nxp.com>
The LPC platforms define memory in SRAM blocks that can be
combined to represent larger memory blocks to the CPU. Change
the M4 allocation to use SRAM0+SRAM1 for 128K.
Signed-off-by: David Leach <david.leach@nxp.com>
LPC platforms define multiple SRAM memory blocks that are contiguous
in memory but the zephyr build system doesn't have a method to
specify all the nodes to be used for a CPU's chosen "zephyr,sram"
node. To be able to get full use of memory, sram0 is redefined to
80KB in size.
Fixes#43872
Signed-off-by: David Leach <david.leach@nxp.com>
remove existing SDMMC SPI driver, since it is replaced by the SPI mode
SD host controller driver.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
with the legacy USDHC driver fully removed from the tree, the
nxp,imx-usdhc binding can now be used for the new SD host controller
driver.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
all in tree SOCs with the USDHC peripheral have now been converted to
use the new SD host controller USDHC driver, so remove legacy NXP disk
USDHC driver.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
added support for NXP iMX RT600/RT500 to use to SDHC driver, with SD
subsystem. Tested with RT685 EVK
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add SDHC driver implementing spi mode support for SD cards. This driver
implements the standard SD host controller APIs, and sets the host
property "is_spi" to indicate to the SD subsystem the card will be
running in SPI mode.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add generic SDHC dts binding, as well as DTS binding for NXP USDHC.
Update iMX.RT DTS binding to use USDHC compatible
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Changes signature so it takes uint32_t instead of pointer to a
register.
Later `sys_read*` and `sys_write*` functions are used, which cast
given address to volatile pointer anyway.
This required changing types of some fields in LiteX GPIO driver and
removal of two casts in clock control driver.
There was a weird assert from LiteX GPIO driver, which checked whether
size of first register in dts was a multiple of 4.
It didn't make much sense, so I removed it.
Previous dts was describing size of a register in terms of subregisters
used. New one uses size of register, so right now it is almost always
4 bytes.
Most drivers don't read register size from dts anyway, so only changes
had to be made in GPIO and clock control drivers.
Both use `litex_read` and `litex_write` to operate on `n`bytes.
Now GPIO driver calculates this `n` value in compile time from given
number of pins and stores it in `reg_size` field of config struct like
before.
Registe sizes in clock control driver are hardcoded, because they are
tied to LiteX wrapper anyway.
This makes it possible to have code, independent of CSR data width.
Signed-off-by: Michal Sieron <msieron@internships.antmicro.com>
Make the LSE driving capability configurable for the STM32 series.
Fixes#44737.
Signed-off-by: Benedikt Schmidt <benedikt.schmidt@embedded-solutions.at>
Fix the descriptions for the ST STM32 FDCAN devicetree bindings. These
are derivates of the Bosch M_CAN, but they target specific SoC
implementations.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Rename the base Bosch M_CAN CAN-FD controller devicetree binding to
match the product name and the upstream Linux devicetree binding.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Fold the simple bosch,m-can devicetree binding into the front-end
devicetree bindings. The bosch,m-can compatible is not used in Zephyr.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
MCP4728 is a 12-bit, Quad Digital-to-Analog Converter with EEPROM Memory.
Controlled via I2C interface.
Signed-off-by: Marek Janus <marek.janus@grinn-global.com>
In 92d8329d5b a new DT property was introduced to set the WQ priority
of the instance. The fallback value when the property was not present
was arbitrarily set to <0 PRIO_PREEMPT>.
The problem is that this value is actually changing the behaviour for
the code that is not explicitly setting the DT property, breaking in
some cases the existing code.
Move the default value to <0 PRIO_COOP> to give the old code a
consistent behaviour before and after the 92d8329d5b commit.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Add a GPIO pass-thru map for accessing the full range (0 to 39) of ESP32
GPIO pins by their datasheet number.
GPIOs 0 to 31 are mapped to gpio0 while GPIOs 32 to 39 are mapped to
gpio1.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
This is a follow-up to commit 1a01ca2adf.
Since support for pinctrl has been added to the qdec_nrfx driver,
the related binding can no longer require the `a-pin` and `b-pin`
properties to be defined.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Add DT option to configure the data ready interrupt mode.
Latched is the default; pulsed can be enabled through
the drdy-pulsed DT, if desired.
Signed-off-by: Maxime Vincent <maxime@veemax.be>
Add FDS (Filtered Data Type Selection) + High-Pass reference mode support
(FDS in CTRL6, HP_REF_MODE in CTRL7)
Values are configurable through DT per instance.
Signed-off-by: Maxime Vincent <maxime@veemax.be>
Henrik Brix Andersen