Commit Graph

6 Commits

Author SHA1 Message Date
Leandro Pereira c78f55d0af boards: esp32: Do not use undefined CONFIG_BOARD_XTENSA
Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
2017-06-21 18:09:13 -04:00
Leandro Pereira f0b4e174d7 esp32: Use esptool.py to flash with 'make flash'
This flashes Zephyr at 0x1000: that's where the first stage bootloader,
part of the ESP32 ROM, expects to find an "image header".

The second-stage bootloader, part of ESP-IDF, isn't used by the Zephyr
port.  However, the bootloader can be used if desired; please refer to
the ESP-IDF documentation on how to set up partitions tables and use
the bootloader.

The following environment variables will affect the ESP32 flashing
process:

  Variable              Default value
  ESP_DEVICE            /dev/ttyUSB0
  ESP_BAUD_RATE         921600
  ESP_FLASH_SIZE        detect
  ESP_FLASH_FREQ        40m
  ESP_FLASH_MODE        dio
  ESP_TOOL              espidf

It's impossible to determine which serial port the ESP32 board is
connected to, as it uses a generic RS232-USB converter.  The default of
/dev/ttyUSB0 is provided as that's often the assigned name on a Linux
machine without any other such converters.

The baud rate of 921600bps is recommended.  If experiencing issues when
flashing, try halving the value a few times (460800, 230400, 115200,
etc).  It might be necessary to change the flash frequency or the flash
mode; please refer to the esptool documentation for guidance on these
settings.

If ${ESP_TOOL} is set to "espidf", the esptool.py script found within
ESP-IDF will be used.  Otherwise, this variable is handled as a path to
the tool.

Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
2017-06-21 12:35:49 -04:00
Leandro Pereira 0e08b946de soc: esp32: Define __start as a C function
The first stage bootloader, part of the ESP32 ROM, already sets up
a stack that's sufficient to execute C programs.  So, instead of
implementing __stack() in assembly, do it in C to simplify things
slightly.

This ESP32-specific initialization will perform the following:

  - Disable the watchdog timer that's enabled by the bootloader
  - Move exception handlers to IRAM
  - Disable normal interrupts
  - Disable the second CPU
  - Zero out the BSS segment

Things that might be performed in the future include setting up the
CPU frequency, memory protection regions, and enabling the flash
cache.

Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
2017-06-21 12:35:49 -04:00
Leandro Pereira 4ca586e62d arch: xtensa: Use Zephyr configuration options
Unconditionally use CONFIG_SIMULATOR_XTENSA to determine if XT_SIMULATOR
or XT_BOARD should be defined.

If CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC, also define XT_CLOCK_FREQ.  This
isn't ideal as the clock frequency might be changed in runtime and this
effectively makes it a constant.

Until we can control the clock frequency in runtime, this will suffice.

Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
2017-06-21 12:35:49 -04:00
Leandro Pereira 37ea77173c drivers: esp32: Add minimal UART driver based on ROM routines
This is a minimal driver enabling console output during the port
bringup.  While the driver works, only one of the three UART devices
are supported, and there isn't any way to change any parameters or
use interrupts.  This will most likely be superceded by a proper
driver after the port has matured.

Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
2017-06-21 12:35:49 -04:00
Leandro Pereira c13174935b boards: xtensa: Add ESP32 board
This is based on the work of Rajavardhan Gundi.

Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
2017-06-21 12:35:49 -04:00