Add Power and clock gating control register to register map and
appropriate bit macros. Add missing GHWCFG4, GLPMCFG and GPWRDN bits.
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
Add all register bit defines necessary for isochronous transfers. Clean
up the endpoint transfer size register defines clearly separating IN and
OUT registers because they do use different bit fields. Add alternate
bit names for bits that do have different meaning based on configured
endpoint transfer type.
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
Make driver aware of High-Bandwidth endpoints both in Completer and
Buffer DMA mode. In Completer mode TxFIFO must be able to hold all
packets for microframe, while in Buffer DMA mode space enough for two
packets is sufficient.
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
This header is based on drivers/usb/device/usb_dw_registers.h and
describes registers of the DWC2 controllers IP and is intended for use
in both device controller drivers and a host controller driver. The
difference to usb_dw_registers.h is that this header does not confuse
offsets with bit positions, contains all the definitions required for
device mode, has register and bit field names identical to the databook
and no annoying underscores.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
Tomasz Moń