drivers: dp: swdp_bitbang: Update SWD clock calculation
This patch updates the SWD clock calculation to the latest behavior of DAPLink. Signed-off-by: Maximilian Deubel <maximilian.deubel@nordicsemi.no>
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@ -26,8 +26,8 @@
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#include <zephyr/logging/log.h>
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LOG_MODULE_REGISTER(swdp, CONFIG_DP_DRIVER_LOG_LEVEL);
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#define CLOCK_DELAY(swclk_freq, port_write_cycles) \
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((CPU_CLOCK / 2 / swclk_freq) - port_write_cycles)
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#define MAX_SWJ_CLOCK(delay_cycles, port_write_cycles) \
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((CPU_CLOCK / 2U) / (port_write_cycles + delay_cycles))
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/*
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* Default SWCLK frequency in Hz.
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@ -35,6 +35,7 @@ LOG_MODULE_REGISTER(swdp, CONFIG_DP_DRIVER_LOG_LEVEL);
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*/
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#define SWDP_DEFAULT_SWCLK_FREQUENCY 1000000U
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#define DELAY_FAST_CYCLES 2U
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#define DELAY_SLOW_CYCLES 3U
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struct sw_config {
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@ -528,14 +529,19 @@ static int sw_set_clock(const struct device *dev, const uint32_t clock)
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struct sw_cfg_data *sw_data = dev->data;
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uint32_t delay;
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sw_data->fast_clock = false;
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delay = ((CPU_CLOCK / 2U) + (clock - 1U)) / clock;
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if (delay > config->port_write_cycles) {
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delay -= config->port_write_cycles;
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delay = (delay + (DELAY_SLOW_CYCLES - 1U)) / DELAY_SLOW_CYCLES;
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} else {
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if (clock >= MAX_SWJ_CLOCK(DELAY_FAST_CYCLES, config->port_write_cycles)) {
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sw_data->fast_clock = true;
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delay = 1U;
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} else {
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sw_data->fast_clock = false;
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delay = ((CPU_CLOCK / 2U) + (clock - 1U)) / clock;
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if (delay > config->port_write_cycles) {
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delay -= config->port_write_cycles;
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delay = (delay + (DELAY_SLOW_CYCLES - 1U)) / DELAY_SLOW_CYCLES;
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} else {
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delay = 1U;
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}
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}
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sw_data->clock_delay = delay;
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@ -666,8 +672,7 @@ static int sw_gpio_init(const struct device *dev)
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sw_data->turnaround = 1U;
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sw_data->data_phase = false;
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sw_data->fast_clock = false;
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sw_data->clock_delay = CLOCK_DELAY(SWDP_DEFAULT_SWCLK_FREQUENCY,
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config->port_write_cycles);
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sw_set_clock(dev, SWDP_DEFAULT_SWCLK_FREQUENCY);
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return 0;
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}
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