drivers: esp32: SDHC implementation
Implementation of SDHC driver for ESP32 Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
This commit is contained in:
Raffael Rostagno
Carles Cufí
parent
b2ae36087b
commit
f4a6fd1f3f
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@ -10,4 +10,5 @@ zephyr_library_sources_ifdef(CONFIG_SAM_HSMCI sam_hsmci.c)
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zephyr_library_sources_ifdef(CONFIG_INTEL_EMMC_HOST intel_emmc_host.c)
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zephyr_library_sources_ifdef(CONFIG_SDHC_INFINEON_CAT1 ifx_cat1_sdio.c)
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zephyr_library_sources_ifdef(CONFIG_CDNS_SDHC sdhc_cdns_ll.c sdhc_cdns.c)
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zephyr_library_sources_ifdef(CONFIG_SDHC_ESP32 sdhc_esp32.c)
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endif()
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@ -15,6 +15,7 @@ source "drivers/sdhc/Kconfig.mcux_sdif"
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source "drivers/sdhc/Kconfig.sam_hsmci"
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source "drivers/sdhc/Kconfig.intel"
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source "drivers/sdhc/Kconfig.sdhc_cdns"
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source "drivers/sdhc/Kconfig.esp32"
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config SDHC_INIT_PRIORITY
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int "SDHC driver init priority"
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@ -0,0 +1,19 @@
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# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
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# SPDX -License-Identifier: Apache-2.0
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config SDHC_ESP32
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bool "ESP32 SDHC Driver"
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default y
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depends on DT_HAS_ESPRESSIF_ESP32_SDHC_SLOT_ENABLED
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select SDHC_SUPPORTS_NATIVE_MODE
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select PINCTRL
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help
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Enables the ESP32 SD Host controller driver
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if SDHC_ESP32
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# ESP32 DMA needs 32 bit aligned buffers
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config SDHC_BUFFER_ALIGNMENT
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default 4
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endif
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File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,132 @@
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/*
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* Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define SDMMC_FREQ_DEFAULT 20000 /*!< SD/MMC Default speed (limited by clock divider) */
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#define SDMMC_FREQ_HIGHSPEED 40000 /*!< SD High speed (limited by clock divider) */
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#define SDMMC_FREQ_PROBING 400 /*!< SD/MMC probing speed */
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#define SDMMC_FREQ_52M 52000 /*!< MMC 52MHz speed */
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#define SDMMC_FREQ_26M 26000 /*!< MMC 26MHz speed */
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#define SDMMC_DATA_ERR_MASK \
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(uint32_t)(SDMMC_INTMASK_DTO | SDMMC_INTMASK_DCRC | SDMMC_INTMASK_HTO | \
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SDMMC_INTMASK_SBE | SDMMC_INTMASK_EBE)
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#define SDMMC_DMA_DONE_MASK \
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(uint32_t)(SDMMC_IDMAC_INTMASK_RI | SDMMC_IDMAC_INTMASK_TI | SDMMC_IDMAC_INTMASK_NI)
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#define SDMMC_CMD_ERR_MASK \
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(uint32_t)(SDMMC_INTMASK_RTO | SDMMC_INTMASK_RCRC | SDMMC_INTMASK_RESP_ERR)
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enum sdmmc_req_state {
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SDMMC_IDLE,
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SDMMC_SENDING_CMD,
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SDMMC_SENDING_DATA,
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SDMMC_BUSY,
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};
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/* SDHC command flags */
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#define SCF_ITSDONE 0x0001 /*!< command is complete */
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#define SCF_CMD(flags) ((flags) & 0x00f0)
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#define SCF_CMD_AC 0x0000
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#define SCF_CMD_ADTC 0x0010
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#define SCF_CMD_BC 0x0020
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#define SCF_CMD_BCR 0x0030
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#define SCF_CMD_READ 0x0040 /*!< read command (data expected) */
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#define SCF_RSP_BSY 0x0100
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#define SCF_RSP_136 0x0200
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#define SCF_RSP_CRC 0x0400
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#define SCF_RSP_IDX 0x0800
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#define SCF_RSP_PRESENT 0x1000
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/* response types */
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#define SCF_RSP_R0 0 /*!< none */
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#define SCF_RSP_R1 (SCF_RSP_PRESENT | SCF_RSP_CRC | SCF_RSP_IDX)
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#define SCF_RSP_R1B (SCF_RSP_PRESENT | SCF_RSP_CRC | SCF_RSP_IDX | SCF_RSP_BSY)
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#define SCF_RSP_R2 (SCF_RSP_PRESENT | SCF_RSP_CRC | SCF_RSP_136)
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#define SCF_RSP_R3 (SCF_RSP_PRESENT)
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#define SCF_RSP_R4 (SCF_RSP_PRESENT)
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#define SCF_RSP_R5 (SCF_RSP_PRESENT | SCF_RSP_CRC | SCF_RSP_IDX)
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#define SCF_RSP_R5B (SCF_RSP_PRESENT | SCF_RSP_CRC | SCF_RSP_IDX | SCF_RSP_BSY)
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#define SCF_RSP_R6 (SCF_RSP_PRESENT | SCF_RSP_CRC | SCF_RSP_IDX)
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#define SCF_RSP_R7 (SCF_RSP_PRESENT | SCF_RSP_CRC | SCF_RSP_IDX)
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/* special flags */
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#define SCF_WAIT_BUSY 0x2000 /*!< Wait for completion of card busy signal before returning */
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#define SD_OCR_SDHC_CAP (1 << 30)
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#define SD_OCR_VOL_MASK 0xFF8000 /* bits 23:15 */
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/* For debug only */
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static const char *const timingStr[] = {"UNKNOWN", "LEGACY", "HS", "SDR12", "SDR25", "SDR50",
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"SDR104", "DDR50", "DDR52", "HS200", "HS400"};
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struct sdmmc_transfer_state {
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uint8_t *ptr;
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size_t size_remaining;
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size_t next_desc;
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size_t desc_remaining;
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};
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struct sdmmc_event {
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uint32_t header_DUMMY; /* Reserved for system use (Zephyr message queue) */
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uint32_t sdmmc_status; /* masked SDMMC interrupt status */
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uint32_t dma_status; /* masked DMA interrupt status */
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};
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/**
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* Host contexts
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*/
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struct host_ctx {
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intr_handle_t intr_handle;
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struct k_msgq *event_queue;
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};
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/**
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* SD/MMC command information
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*/
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struct sdmmc_command {
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uint32_t opcode; /*!< SD or MMC command index */
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uint32_t arg; /*!< SD/MMC command argument */
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uint32_t response[4]; /*!< response buffer */
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void *data; /*!< buffer to send or read into */
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size_t datalen; /*!< length of data in the buffer */
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size_t buflen; /*!< length of the buffer */
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size_t blklen; /*!< block length */
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int flags; /*!< see below */
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esp_err_t error; /*!< error returned from transfer */
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uint32_t timeout_ms; /*!< response timeout, in milliseconds */
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};
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/**
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* @brief Convert ESP to Zephyr error codes
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*
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* @param ret_esp ESP return value
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*
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* @return Zephyr error code
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*/
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static __attribute__((always_inline)) inline int err_esp2zep(int ret_esp)
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{
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int ret;
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switch (ret_esp) {
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/* Treating the error codes most relevant to be individuated */
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case ESP_ERR_INVALID_ARG:
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ret = -EINVAL;
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break;
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case ESP_ERR_TIMEOUT:
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ret = -ETIMEDOUT;
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break;
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case ESP_ERR_NOT_FOUND:
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ret = -ENODEV; /* SD card not inserted (requires CD signal) */
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break;
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case ESP_ERR_INVALID_STATE:
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ret = -EACCES; /* SD card write-protected (requires WP sinal) */
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break;
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default:
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ret = -EIO;
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break;
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}
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return ret;
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}
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@ -0,0 +1,76 @@
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# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
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# SPDX-License-Identifier: Apache-2.0
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description: Espressif ESP32 SDHC controller slot
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compatible: "espressif,esp32-sdhc-slot"
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include: [sdhc.yaml, pinctrl-device.yaml]
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properties:
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reg:
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required: true
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pinctrl-0:
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required: true
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pinctrl-names:
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required: true
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bus-width:
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type: int
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enum:
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- 1
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- 4
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default: 4
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description: SD bus width in bits
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clk-pin:
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type: int
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description: |
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Clock pin for ESP32 and SoC models with fixed pins for SDIO.
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For devices with GPIO matrix support, configuration shall be done
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using pin control (pinctrl-0 field).
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cmd-pin:
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type: int
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description: |
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Command pin for ESP32 and SoC models with fixed pins for SDIO.
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For devices with GPIO matrix support, configuration shall be done
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using pin control (pinctrl-0 field).
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d0-pin:
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type: int
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description: |
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Data 0 pin for ESP32 and SoC models with fixed pins for SDIO.
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For devices with GPIO matrix support, configuration shall be done
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using pin control (pinctrl-0 field).
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d1-pin:
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type: int
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description: |
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Data 1 pin for ESP32 and SoC models with fixed pins for SDIO.
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For devices with GPIO matrix support, configuration shall be done
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using pin control (pinctrl-0 field).
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d2-pin:
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type: int
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description: |
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Data 2 pin for ESP32 and SoC models with fixed pins for SDIO.
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For devices with GPIO matrix support, configuration shall be done
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using pin control (pinctrl-0 field).
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d3-pin:
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type: int
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description: |
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Data 3 pin for ESP32 and SoC models with fixed pins for SDIO.
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For devices with GPIO matrix support, configuration shall be done
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using pin control (pinctrl-0 field).
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pwr-gpios:
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type: phandle-array
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description: |
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Power pin
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This is a configurable pin to deliver power supply to the SD card.
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It is configured as a GPIO in order to execute power toggles and
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reinitialize the SD slave when necessary.
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@ -0,0 +1,15 @@
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# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
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# SPDX-License-Identifier: Apache-2.0
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description: Espressif ESP32 SDHC controller
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compatible: "espressif,esp32-sdhc"
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include: [base.yaml]
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properties:
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reg:
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required: true
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interrupts:
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required: true
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@ -425,5 +425,26 @@
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status = "disabled";
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};
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sdhc: sdhc@3ff68000 {
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compatible = "espressif,esp32-sdhc";
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reg = <0x3ff68000 0x1000>;
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interrupts = <SDIO_HOST_INTR_SOURCE>;
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interrupt-parent = <&intc>;
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clocks = <&rtc ESP32_SDMMC_MODULE>;
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#address-cells = <1>;
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#size-cells = <0>;
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sdhc0: sdhc@0 {
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compatible = "espressif,esp32-sdhc-slot";
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reg = <0>;
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status = "disabled";
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};
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sdhc1: sdhc@1 {
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compatible = "espressif,esp32-sdhc-slot";
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reg = <1>;
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status = "disabled";
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};
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};
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};
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};
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@ -8133,6 +8133,164 @@
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#define PCNT7_CH1SIG_GPIO39 \
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ESP32_PINMUX(39, ESP_PCNT_SIG_CH1_IN7, ESP_NOSIG)
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/* SDHC0_CD */
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#define SDHC0_CD_GPIO5 \
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ESP32_PINMUX(5, ESP_HOST_CARD_DETECT_N_2, ESP_NOSIG)
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#define SDHC0_CD_GPIO6 \
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ESP32_PINMUX(6, ESP_HOST_CARD_DETECT_N_2, ESP_NOSIG)
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#define SDHC0_CD_GPIO7 \
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ESP32_PINMUX(7, ESP_HOST_CARD_DETECT_N_2, ESP_NOSIG)
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#define SDHC0_CD_GPIO8 \
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ESP32_PINMUX(8, ESP_HOST_CARD_DETECT_N_2, ESP_NOSIG)
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#define SDHC0_CD_GPIO9 \
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ESP32_PINMUX(9, ESP_HOST_CARD_DETECT_N_2, ESP_NOSIG)
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#define SDHC0_CD_GPIO10 \
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ESP32_PINMUX(10, ESP_HOST_CARD_DETECT_N_2, ESP_NOSIG)
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#define SDHC0_CD_GPIO11 \
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ESP32_PINMUX(11, ESP_HOST_CARD_DETECT_N_2, ESP_NOSIG)
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#define SDHC0_CD_GPIO16 \
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ESP32_PINMUX(16, ESP_HOST_CARD_DETECT_N_2, ESP_NOSIG)
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#define SDHC0_CD_GPIO17 \
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ESP32_PINMUX(17, ESP_HOST_CARD_DETECT_N_2, ESP_NOSIG)
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#define SDHC0_CD_GPIO18 \
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ESP32_PINMUX(18, ESP_HOST_CARD_DETECT_N_2, ESP_NOSIG)
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#define SDHC0_CD_GPIO19 \
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ESP32_PINMUX(19, ESP_HOST_CARD_DETECT_N_2, ESP_NOSIG)
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#define SDHC0_CD_GPIO20 \
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ESP32_PINMUX(20, ESP_HOST_CARD_DETECT_N_2, ESP_NOSIG)
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#define SDHC0_CD_GPIO21 \
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ESP32_PINMUX(21, ESP_HOST_CARD_DETECT_N_2, ESP_NOSIG)
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#define SDHC0_CD_GPIO22 \
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ESP32_PINMUX(22, ESP_HOST_CARD_DETECT_N_2, ESP_NOSIG)
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#define SDHC0_CD_GPIO23 \
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ESP32_PINMUX(23, ESP_HOST_CARD_DETECT_N_2, ESP_NOSIG)
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#define SDHC0_CD_GPIO25 \
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ESP32_PINMUX(25, ESP_HOST_CARD_DETECT_N_2, ESP_NOSIG)
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#define SDHC0_CD_GPIO26 \
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ESP32_PINMUX(26, ESP_HOST_CARD_DETECT_N_2, ESP_NOSIG)
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#define SDHC0_CD_GPIO27 \
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ESP32_PINMUX(27, ESP_HOST_CARD_DETECT_N_2, ESP_NOSIG)
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#define SDHC0_CD_GPIO32 \
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ESP32_PINMUX(32, ESP_HOST_CARD_DETECT_N_2, ESP_NOSIG)
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#define SDHC0_CD_GPIO33 \
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ESP32_PINMUX(33, ESP_HOST_CARD_DETECT_N_2, ESP_NOSIG)
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#define SDHC0_CD_GPIO34 \
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ESP32_PINMUX(34, ESP_HOST_CARD_DETECT_N_2, ESP_NOSIG)
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#define SDHC0_CD_GPIO35 \
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ESP32_PINMUX(35, ESP_HOST_CARD_DETECT_N_2, ESP_NOSIG)
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#define SDHC0_CD_GPIO36 \
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ESP32_PINMUX(36, ESP_HOST_CARD_DETECT_N_2, ESP_NOSIG)
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#define SDHC0_CD_GPIO37 \
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ESP32_PINMUX(37, ESP_HOST_CARD_DETECT_N_2, ESP_NOSIG)
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#define SDHC0_CD_GPIO38 \
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ESP32_PINMUX(38, ESP_HOST_CARD_DETECT_N_2, ESP_NOSIG)
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#define SDHC0_CD_GPIO39 \
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ESP32_PINMUX(39, ESP_HOST_CARD_DETECT_N_2, ESP_NOSIG)
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/* SDHC0_WP */
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#define SDHC0_WP_GPIO5 \
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ESP32_PINMUX(5, ESP_HOST_CARD_WRITE_PRT_2, ESP_NOSIG)
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#define SDHC0_WP_GPIO6 \
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ESP32_PINMUX(6, ESP_HOST_CARD_WRITE_PRT_2, ESP_NOSIG)
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#define SDHC0_WP_GPIO7 \
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ESP32_PINMUX(7, ESP_HOST_CARD_WRITE_PRT_2, ESP_NOSIG)
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#define SDHC0_WP_GPIO8 \
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ESP32_PINMUX(8, ESP_HOST_CARD_WRITE_PRT_2, ESP_NOSIG)
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#define SDHC0_WP_GPIO9 \
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ESP32_PINMUX(9, ESP_HOST_CARD_WRITE_PRT_2, ESP_NOSIG)
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#define SDHC0_WP_GPIO10 \
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ESP32_PINMUX(10, ESP_HOST_CARD_WRITE_PRT_2, ESP_NOSIG)
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#define SDHC0_WP_GPIO11 \
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ESP32_PINMUX(11, ESP_HOST_CARD_WRITE_PRT_2, ESP_NOSIG)
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#define SDHC0_WP_GPIO16 \
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ESP32_PINMUX(16, ESP_HOST_CARD_WRITE_PRT_2, ESP_NOSIG)
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#define SDHC0_WP_GPIO17 \
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ESP32_PINMUX(17, ESP_HOST_CARD_WRITE_PRT_2, ESP_NOSIG)
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#define SDHC0_WP_GPIO18 \
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ESP32_PINMUX(18, ESP_HOST_CARD_WRITE_PRT_2, ESP_NOSIG)
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#define SDHC0_WP_GPIO19 \
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ESP32_PINMUX(19, ESP_HOST_CARD_WRITE_PRT_2, ESP_NOSIG)
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#define SDHC0_WP_GPIO20 \
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ESP32_PINMUX(20, ESP_HOST_CARD_WRITE_PRT_2, ESP_NOSIG)
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#define SDHC0_WP_GPIO21 \
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ESP32_PINMUX(21, ESP_HOST_CARD_WRITE_PRT_2, ESP_NOSIG)
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#define SDHC0_WP_GPIO22 \
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ESP32_PINMUX(22, ESP_HOST_CARD_WRITE_PRT_2, ESP_NOSIG)
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#define SDHC0_WP_GPIO23 \
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ESP32_PINMUX(23, ESP_HOST_CARD_WRITE_PRT_2, ESP_NOSIG)
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#define SDHC0_WP_GPIO25 \
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ESP32_PINMUX(25, ESP_HOST_CARD_WRITE_PRT_2, ESP_NOSIG)
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#define SDHC0_WP_GPIO26 \
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ESP32_PINMUX(26, ESP_HOST_CARD_WRITE_PRT_2, ESP_NOSIG)
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#define SDHC0_WP_GPIO27 \
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ESP32_PINMUX(27, ESP_HOST_CARD_WRITE_PRT_2, ESP_NOSIG)
|
||||
|
||||
#define SDHC0_WP_GPIO32 \
|
||||
ESP32_PINMUX(32, ESP_HOST_CARD_WRITE_PRT_2, ESP_NOSIG)
|
||||
|
||||
#define SDHC0_WP_GPIO33 \
|
||||
ESP32_PINMUX(33, ESP_HOST_CARD_WRITE_PRT_2, ESP_NOSIG)
|
||||
|
||||
#define SDHC0_WP_GPIO34 \
|
||||
ESP32_PINMUX(34, ESP_HOST_CARD_WRITE_PRT_2, ESP_NOSIG)
|
||||
|
||||
#define SDHC0_WP_GPIO35 \
|
||||
ESP32_PINMUX(35, ESP_HOST_CARD_WRITE_PRT_2, ESP_NOSIG)
|
||||
|
||||
#define SDHC0_WP_GPIO36 \
|
||||
ESP32_PINMUX(36, ESP_HOST_CARD_WRITE_PRT_2, ESP_NOSIG)
|
||||
|
||||
#define SDHC0_WP_GPIO37 \
|
||||
ESP32_PINMUX(37, ESP_HOST_CARD_WRITE_PRT_2, ESP_NOSIG)
|
||||
|
||||
#define SDHC0_WP_GPIO38 \
|
||||
ESP32_PINMUX(38, ESP_HOST_CARD_WRITE_PRT_2, ESP_NOSIG)
|
||||
|
||||
#define SDHC0_WP_GPIO39 \
|
||||
ESP32_PINMUX(39, ESP_HOST_CARD_WRITE_PRT_2, ESP_NOSIG)
|
||||
|
||||
/* SMI_MDC */
|
||||
#define SMI_MDC_GPIO0 \
|
||||
ESP32_PINMUX(0, ESP_NOSIG, ESP_EMAC_MDC_O)
|
||||
|
|
|
|||
Loading…
Reference in New Issue