From eec068b8a51cc618c171f89d381ddb61fddbf272 Mon Sep 17 00:00:00 2001
From: Sylvio Alves <sylvio.alves@espressif.com>
Date: Mon, 17 Jan 2022 23:32:24 -0300
Subject: [PATCH] soc: esp32c3: fix cpu vendor name

Build shows warning due to incompatible
CPU vendor name. This fixes it and applies
necessary changes in files.

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
---
 drivers/clock_control/clock_control_esp32.c | 2 +-
 dts/bindings/cpu/espressif,riscv.yml        | 2 +-
 dts/riscv/espressif/esp32c3.dtsi            | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/clock_control/clock_control_esp32.c b/drivers/clock_control/clock_control_esp32.c
index e72e2a7a40b..40f3ccf0433 100644
--- a/drivers/clock_control/clock_control_esp32.c
+++ b/drivers/clock_control/clock_control_esp32.c
@@ -21,7 +21,7 @@
 #include <dt-bindings/clock/esp32s2_clock.h>
 #include "esp32s2/rom/rtc.h"
 #elif CONFIG_IDF_TARGET_ESP32C3
-#define DT_CPU_COMPAT esp_riscv
+#define DT_CPU_COMPAT espressif_riscv
 #include <dt-bindings/clock/esp32c3_clock.h>
 #include "esp32c3/rom/rtc.h"
 #include <soc/soc_caps.h>
diff --git a/dts/bindings/cpu/espressif,riscv.yml b/dts/bindings/cpu/espressif,riscv.yml
index 41dbb7481bc..387fdac2797 100644
--- a/dts/bindings/cpu/espressif,riscv.yml
+++ b/dts/bindings/cpu/espressif,riscv.yml
@@ -3,7 +3,7 @@
 
 description: Espressif RISC-V CPU
 
-compatible: "esp,riscv"
+compatible: "espressif,riscv"
 
 include: cpu.yaml
 
diff --git a/dts/riscv/espressif/esp32c3.dtsi b/dts/riscv/espressif/esp32c3.dtsi
index f3fd1d79489..54e6ebad441 100644
--- a/dts/riscv/espressif/esp32c3.dtsi
+++ b/dts/riscv/espressif/esp32c3.dtsi
@@ -24,7 +24,7 @@
 
 		cpu0: cpu@0 {
 			device_type = "cpu";
-			compatible = "esp,riscv";
+			compatible = "espressif,riscv";
 			reg = <0>;
 		};
 	};