diff --git a/boards/st/nucleo_h745zi_q/doc/index.rst b/boards/st/nucleo_h745zi_q/doc/index.rst
index ba3f5627a6f..39a74a81ab7 100644
--- a/boards/st/nucleo_h745zi_q/doc/index.rst
+++ b/boards/st/nucleo_h745zi_q/doc/index.rst
@@ -112,6 +112,8 @@ features:
 +-------------+------------+-------------------------------------+
 | SPI         | on-chip    | spi                                 |
 +-------------+------------+-------------------------------------+
+| FDCAN       | on-chip    | CAN-FD Control Area Network         |
++-------------+------------+-------------------------------------+
 
 Other hardware features are not yet supported on this Zephyr port.
 
diff --git a/boards/st/nucleo_h745zi_q/nucleo_h745zi_q_stm32h745xx_m7.dts b/boards/st/nucleo_h745zi_q/nucleo_h745zi_q_stm32h745xx_m7.dts
index bce218ae37d..b9ddb37cb79 100644
--- a/boards/st/nucleo_h745zi_q/nucleo_h745zi_q_stm32h745xx_m7.dts
+++ b/boards/st/nucleo_h745zi_q/nucleo_h745zi_q_stm32h745xx_m7.dts
@@ -144,3 +144,14 @@ zephyr_udc0: &usbotg_fs {
 	pinctrl-names = "default";
 	status = "okay";
 };
+
+&fdcan1 {
+	pinctrl-0 = <&fdcan1_rx_pd0 &fdcan1_tx_pd1>;
+	/* HSE will be used by default. Uncomment below to enable APB1.2 120MHz clock */
+	/*
+	 * clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000100>,
+	 *	   <&rcc STM32_SRC_PLL1_Q FDCAN_SEL(1)>;
+	 */
+	pinctrl-names = "default";
+	status = "okay";
+};
diff --git a/boards/st/nucleo_h745zi_q/nucleo_h745zi_q_stm32h745xx_m7.yaml b/boards/st/nucleo_h745zi_q/nucleo_h745zi_q_stm32h745xx_m7.yaml
index ff551e71837..259cd29438b 100644
--- a/boards/st/nucleo_h745zi_q/nucleo_h745zi_q_stm32h745xx_m7.yaml
+++ b/boards/st/nucleo_h745zi_q/nucleo_h745zi_q_stm32h745xx_m7.yaml
@@ -16,6 +16,7 @@ supported:
   - counter
   - i2c
   - pwm
+  - can
   - netif:eth
   - spi
   - usb_device