From e30d78c7645518aae5536eb727efbe32386aaf39 Mon Sep 17 00:00:00 2001 From: Georgij Cernysiov Date: Tue, 22 Nov 2022 19:19:24 +0100 Subject: [PATCH] dts: bindings: clock: fix stm32h7 div-m description Divider value shall start from 1. Signed-off-by: Georgij Cernysiov --- dts/bindings/clock/st,stm32h7-pll-clock.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/dts/bindings/clock/st,stm32h7-pll-clock.yaml b/dts/bindings/clock/st,stm32h7-pll-clock.yaml index 8b4e9d5d105..702e92cec71 100644 --- a/dts/bindings/clock/st,stm32h7-pll-clock.yaml +++ b/dts/bindings/clock/st,stm32h7-pll-clock.yaml @@ -39,7 +39,7 @@ properties: description: | Division factor for PLLx input clock - Valid range: 0 - 63 + Valid range: 1 - 63 mul-n: type: int