dts: bindings: clock: fix stm32h7 div-m description

Divider value shall start from 1. Signed-off-by: Georgij Cernysiov <geo.cgv@gmail.com>
2022-11-22 19:19:24 +01:00 · 2022-11-22 19:19:24 +01:00 · e30d78c764
parent a78bdbce89
commit e30d78c764
1 changed files with 1 additions and 1 deletions
--- a/dts/bindings/clock/st,stm32h7-pll-clock.yaml
+++ b/dts/bindings/clock/st,stm32h7-pll-clock.yaml
@ -39,7 +39,7 @@ properties:
      description: |
          Division factor for PLLx
          input clock
-          Valid range: 0 - 63
+          Valid range: 1 - 63

    mul-n:
      type: int