From dd60d800d02fd99b8b08d0cbfc5e66b5e82c628e Mon Sep 17 00:00:00 2001 From: Evgeniy Paltsev Date: Wed, 11 May 2022 18:17:04 +0400 Subject: [PATCH] doc: ARC: update ARC HW & tools support status List of the changes: * add info about ARCv3 32bit HS5x which support has been upstreamed recently * mark HS6x MWDT toolchain support as Y Signed-off-by: Evgeniy Paltsev Signed-off-by: Eugeniy Paltsev --- doc/hardware/arch/arc-support-status.rst | 106 +++++++++++------------ 1 file changed, 52 insertions(+), 54 deletions(-) diff --git a/doc/hardware/arch/arc-support-status.rst b/doc/hardware/arch/arc-support-status.rst index 77c901aa2e1..9d51460027a 100644 --- a/doc/hardware/arch/arc-support-status.rst +++ b/doc/hardware/arch/arc-support-status.rst @@ -20,57 +20,57 @@ Legend: **TBD** - to be decided -+---------------------------------------------------------------------+------------+-------------+--------+------------+ -| | **Processor families** | -+---------------------------------------------------------------------+------------+-------------+--------+------------+ -| | **EM** | **HS3x/4x** | **EV** | **HS6x** | -+---------------------------------------------------------------------+------------+-------------+--------+------------+ -| Port status | upstreamed | upstreamed | WIP | upstreamed | -+---------------------------------------------------------------------+------------+-------------+--------+------------+ -| **Features** | -+---------------------------------------------------------------------+------------+-------------+--------+------------+ -| Closely coupled memories (ICCM, DCCM) [#f1]_ | Y | Y | TBD | TBD | -+---------------------------------------------------------------------+------------+-------------+--------+------------+ -| Execution with caches - Instruction/Data, L1/L2 caches | Y | Y | Y | Y | -+---------------------------------------------------------------------+------------+-------------+--------+------------+ -| Hardware-assisted unaligned memory access | Y [#f2]_ | Y | TBD | Y | -+---------------------------------------------------------------------+------------+-------------+--------+------------+ -| Regular interrupts with multiple priority levels, direct interrupts | Y | Y | TBD | Y | -+---------------------------------------------------------------------+------------+-------------+--------+------------+ -| Fast interrupts, separate register banks for fast interrupts | Y | Y | TBD | N | -+---------------------------------------------------------------------+------------+-------------+--------+------------+ -| Hardware floating point unit (FPU) | Y | Y | N | TBD | -+---------------------------------------------------------------------+------------+-------------+--------+------------+ -| Symmetric multiprocessing (SMP) support, switch-based | N/A | Y | TBD | Y | -+---------------------------------------------------------------------+------------+-------------+--------+------------+ -| Hardware-assisted stack checking | Y | Y | TBD | N | -+---------------------------------------------------------------------+------------+-------------+--------+------------+ -| Hardware-assisted atomic operations | N/A | Y | TBD | Y | -+---------------------------------------------------------------------+------------+-------------+--------+------------+ -| DSP ISA | Y | N [#f3]_ | TBD | TBD | -+---------------------------------------------------------------------+------------+-------------+--------+------------+ -| DSP AGU/XY extensions | N [#f3]_ | N [#f3]_ | TBD | TBD | -+---------------------------------------------------------------------+------------+-------------+--------+------------+ -| Userspace | Y | Y | N | TBD | -+---------------------------------------------------------------------+------------+-------------+--------+------------+ -| Memory protection unit (MPU) | Y | Y | TBD | N | -+---------------------------------------------------------------------+------------+-------------+--------+------------+ -| Memory management unit (MMU) | N/A | N | N/A | N | -+---------------------------------------------------------------------+------------+-------------+--------+------------+ -| SecureShield | Y | N/A | N/A | N/A | -+---------------------------------------------------------------------+------------+-------------+--------+------------+ -| **Toolchains** | -+---------------------------------------------------------------------+------------+-------------+--------+------------+ -| GNU (open source GCC-based) | Y | Y | N | Y | -+---------------------------------------------------------------------+------------+-------------+--------+------------+ -| MetaWare (proprietary Clang-based) | Y | Y | Y | WIP [#f4]_ | -+---------------------------------------------------------------------+------------+-------------+--------+------------+ -| **Simulators** | -+---------------------------------------------------------------------+------------+-------------+--------+------------+ -| QEMU (open source) [#f5]_ | Y | Y | N | Y | -+---------------------------------------------------------------------+------------+-------------+--------+------------+ -| nSIM (proprietary, provided by MetaWare Development Tools) | Y | Y | Y | Y | -+---------------------------------------------------------------------+------------+-------------+--------+------------+ ++---------------------------------------------------------------------+------------+-------------+--------+------------+------------+ +| | **Processor families** | ++---------------------------------------------------------------------+------------+-------------+--------+------------+------------+ +| | **EM** | **HS3x/4x** | **EV** | **HS5x** | **HS6x** | ++---------------------------------------------------------------------+------------+-------------+--------+------------+------------+ +| Port status | upstreamed | upstreamed | WIP | upstreamed | upstreamed | ++---------------------------------------------------------------------+------------+-------------+--------+------------+------------+ +| **Features** | ++---------------------------------------------------------------------+------------+-------------+--------+------------+------------+ +| Closely coupled memories (ICCM, DCCM) [#f1]_ | Y | Y | TBD | TBD | TBD | ++---------------------------------------------------------------------+------------+-------------+--------+------------+------------+ +| Execution with caches - Instruction/Data, L1/L2 caches | Y | Y | Y | Y | Y | ++---------------------------------------------------------------------+------------+-------------+--------+------------+------------+ +| Hardware-assisted unaligned memory access | Y [#f2]_ | Y | TBD | Y | Y | ++---------------------------------------------------------------------+------------+-------------+--------+------------+------------+ +| Regular interrupts with multiple priority levels, direct interrupts | Y | Y | TBD | Y | Y | ++---------------------------------------------------------------------+------------+-------------+--------+------------+------------+ +| Fast interrupts, separate register banks for fast interrupts | Y | Y | TBD | N | N | ++---------------------------------------------------------------------+------------+-------------+--------+------------+------------+ +| Hardware floating point unit (FPU) | Y | Y | N | TBD | TBD | ++---------------------------------------------------------------------+------------+-------------+--------+------------+------------+ +| Symmetric multiprocessing (SMP) support, switch-based | N/A | Y | TBD | Y | Y | ++---------------------------------------------------------------------+------------+-------------+--------+------------+------------+ +| Hardware-assisted stack checking | Y | Y | TBD | N | N | ++---------------------------------------------------------------------+------------+-------------+--------+------------+------------+ +| Hardware-assisted atomic operations | N/A | Y | TBD | Y | Y | ++---------------------------------------------------------------------+------------+-------------+--------+------------+------------+ +| DSP ISA | Y | N [#f3]_ | TBD | TBD | TBD | ++---------------------------------------------------------------------+------------+-------------+--------+------------+------------+ +| DSP AGU/XY extensions | N [#f3]_ | N [#f3]_ | TBD | TBD | TBD | ++---------------------------------------------------------------------+------------+-------------+--------+------------+------------+ +| Userspace | Y | Y | N | TBD | TBD | ++---------------------------------------------------------------------+------------+-------------+--------+------------+------------+ +| Memory protection unit (MPU) | Y | Y | TBD | N | N | ++---------------------------------------------------------------------+------------+-------------+--------+------------+------------+ +| Memory management unit (MMU) | N/A | N | N/A | N | N | ++---------------------------------------------------------------------+------------+-------------+--------+------------+------------+ +| SecureShield | Y | N/A | N/A | N/A | N/A | ++---------------------------------------------------------------------+------------+-------------+--------+------------+------------+ +| **Toolchains** | ++---------------------------------------------------------------------+------------+-------------+--------+------------+------------+ +| GNU (open source GCC-based) | Y | Y | N | Y | Y | ++---------------------------------------------------------------------+------------+-------------+--------+------------+------------+ +| MetaWare (proprietary Clang-based) | Y | Y | Y | Y | Y | ++---------------------------------------------------------------------+------------+-------------+--------+------------+------------+ +| **Simulators** | ++---------------------------------------------------------------------+------------+-------------+--------+------------+------------+ +| QEMU (open source) [#f4]_ | Y | Y | N | Y | Y | ++---------------------------------------------------------------------+------------+-------------+--------+------------+------------+ +| nSIM (proprietary, provided by MetaWare Development Tools) | Y | Y | Y | Y | Y | ++---------------------------------------------------------------------+------------+-------------+--------+------------+------------+ Notes ***** @@ -82,7 +82,5 @@ Notes Rest of DSP/AGU registers save/restore isn't implemented but kernel itself does not use these registers. This allows single task per core to use DSP/AGU safely. -.. [#f4] MetaWare toolchain supports building for ARCv3 HS6x, however, it's - not integrated to Zephyr itself -.. [#f5] QEMU doesn't support all the ARC processor's HW features. For the +.. [#f4] QEMU doesn't support all the ARC processor's HW features. For the detailed info please check the ARC QEMU documentation