soc: nordic: vpr: add workaround for MSTATUS.MIE not waking VPR up
Due to HW issue, VPR needs to keep MSTATUS.MIE enabled during sleep. Otherwise, interrupts will not wake it up. Signed-off-by: Marcin Szymczyk <marcin.szymczyk@nordicsemi.no>
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@ -3,6 +3,6 @@
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zephyr_include_directories(.)
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zephyr_library_sources(soc_irq.S soc_irq.c vector.S)
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zephyr_library_sources(soc_idle.c soc_irq.S soc_irq.c vector.S)
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set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/riscv/common/linker.ld CACHE INTERNAL "")
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@ -15,5 +15,6 @@ config RISCV_CORE_NORDIC_VPR
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select RISCV_SOC_HAS_ISR_STACKING
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select RISCV_SOC_CONTEXT_SAVE
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select HAS_FLASH_LOAD_OFFSET
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select ARCH_CPU_IDLE_CUSTOM
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help
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Enable support for the RISC-V Nordic VPR core.
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@ -0,0 +1,31 @@
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/*
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* Copyright (C) 2024 Nordic Semiconductor ASA
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/irq.h>
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#include <zephyr/tracing/tracing.h>
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/*
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* Due to a HW issue, VPR requires MSTATUS.MIE to be enabled when entering sleep.
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* Otherwise it would not wake up.
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*/
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void arch_cpu_idle(void)
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{
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sys_trace_idle();
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irq_unlock(MSTATUS_IEN);
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__asm__ volatile("wfi");
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}
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void arch_cpu_atomic_idle(unsigned int key)
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{
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sys_trace_idle();
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irq_unlock(MSTATUS_IEN);
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__asm__ volatile("wfi");
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/* Disable interrupts if needed. */
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__asm__ volatile ("csrc mstatus, %0"
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:
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: "r" (~key & MSTATUS_IEN)
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: "memory");
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}
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