From d2072f0502426a34d82eaa788fcf118c80fc0475 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Benjamin=20Cab=C3=A9?= Date: Fri, 18 Oct 2024 16:49:35 +0200 Subject: [PATCH] boards: toradex: adopt new zephyr:board directive and role MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This updates the documentation of all the Toradex boards to use the new `zephyr:board::` directive. Signed-off-by: Benjamin Cabé --- boards/toradex/colibri_imx7d/doc/index.rst | 10 +--------- boards/toradex/verdin_imx8mp/doc/index.rst | 11 +---------- 2 files changed, 2 insertions(+), 19 deletions(-) diff --git a/boards/toradex/colibri_imx7d/doc/index.rst b/boards/toradex/colibri_imx7d/doc/index.rst index dd13a140b3c..ea36ff6b50b 100644 --- a/boards/toradex/colibri_imx7d/doc/index.rst +++ b/boards/toradex/colibri_imx7d/doc/index.rst @@ -1,7 +1,4 @@ -.. _colibri_imx7d: - -NXP i.MX 7 Computer on Module - Colibri iMX7 -############################################ +.. zephyr:board:: colibri_imx7d Overview ******** @@ -11,11 +8,6 @@ core and Single Cortex M4 core. Zephyr was ported to run on the M4 core. In a later release, it will also communicate with the A7 core (running Linux) via RPmsg. - -.. image:: colibri_imx7d.jpg - :align: center - :alt: Colibri-iMX7 - Hardware ******** diff --git a/boards/toradex/verdin_imx8mp/doc/index.rst b/boards/toradex/verdin_imx8mp/doc/index.rst index e59101fa212..af78ea49808 100644 --- a/boards/toradex/verdin_imx8mp/doc/index.rst +++ b/boards/toradex/verdin_imx8mp/doc/index.rst @@ -1,7 +1,4 @@ -.. _verdin_imx8mp: - -Toradex Verdin iMX8M Plus SoM -############################# +.. zephyr:board:: verdin_imx8mp Overview ******** @@ -34,12 +31,6 @@ Quoting NXP: The Verdin iMX8M Plus integrates a total of 4 Arm Cortex™-A53 CPUs, operating at 1.6 GHz, alongside a single Arm Cortex™-M7F microcontroller operating at 800 MHz. -.. figure:: verdin_imx8mp_front.jpg - :align: center - :alt: Toradex Verdin iMX8M Plus - - Toradex Verdin iMX8M Plus (Credit: Toradex) - Regarding the Cortex-A53 cluster, it employs the ARMv8-A architecture as a mid-range and energy-efficient processor. With four cores in this cluster, each core is equipped with its own L1 memory system. Moreover, the cluster incorporates a unified L2 cache that offers supplementary