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boards: mps3: Add support for corstone310/an555 

What is changed?
 - Added a new mps3 board an555 for the soc corstone310.
   The qualifier to build/run application with board mps3/an555 is
   `mps3/corstone310/an555` for secure and
   `mps3/corstone310/an555/ns` for non-secure.
 - Added FVP variant to enable FVP testing with corstone310
   and it uses the ARM FVP `FVP_Corstone_SSE-310`.
   The qualifier to build/run application with FVP is
   `mps3/corstone310/an555fvp` for secure and
   `mps3/corstone310/an555fvp/ns` for non-secure.

Why do we need this change?
 - This enables FVP support and testing for corstone310.
 - A separate FVP variant was added for AN555 because, the TFM board
   used for non-secure variant differs for FPGA and FVP.
   TFM board `arm/mps3/corstone310/an555` should be used when testing
   AN555 with FVP and `arm/mps3/corstone310/fvp` should be used when
   testing with AN555 FPGA.

Signed-off-by: Sudan Landge <sudan.landge@arm.com>
This commit is contained in:
Sudan Landge 2024-09-20 14:26:17 +01:00 committed by David Leach
parent 3092d96e5b
commit caa7226157
22 changed files with 677 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
boards/arm/mps3/Kconfig.defconfig
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@ -2,7 +2,7 @@
# Copyright 2024 Arm Limited and/or its affiliates <open-source-office@arm.com>
# SPDX-License-Identifier: Apache-2.0
if BOARD_MPS3_CORSTONE300_AN547 || BOARD_MPS3_CORSTONE300_AN552 || BOARD_MPS3_CORSTONE300_FVP
if BOARD_MPS3_CORSTONE300_AN547 || BOARD_MPS3_CORSTONE300_AN552 || BOARD_MPS3_CORSTONE300_FVP || BOARD_MPS3_CORSTONE310_AN555 || BOARD_MPS3_CORSTONE310_FVP
# MPU-based null-pointer dereferencing detection cannot
# be applied as the (0x0 - 0x400) is unmapped but QEMU

4
boards/arm/mps3/Kconfig.mps3
View File

@ -11,3 +11,7 @@ config BOARD_MPS3
BOARD_MPS3_CORSTONE300_AN552_NS || \
BOARD_MPS3_CORSTONE300_FVP || \
BOARD_MPS3_CORSTONE300_FVP_NS
select SOC_MPS3_CORSTONE310 if BOARD_MPS3_CORSTONE310_AN555 || \
BOARD_MPS3_CORSTONE310_AN555_NS || \
BOARD_MPS3_CORSTONE310_FVP || \
BOARD_MPS3_CORSTONE310_FVP_NS

10
boards/arm/mps3/board.cmake
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@ -8,6 +8,7 @@
# Default emulation:
# QEMU is used by default for corstone300/an547 and
# FVP is used by default for corstone300/fvp.
# FVP is used by default for corstone310/fvp.
#
@ -29,6 +30,15 @@ elseif(CONFIG_BOARD_MPS3_CORSTONE300)
string(REPLACE "mps3/corstone300;" "" board_targets "${board_targets}")
string(REPLACE ";" "\n" board_targets "${board_targets}")
message(FATAL_ERROR "Please use a target from the list below: \n${board_targets}\n")
elseif(CONFIG_BOARD_MPS3_CORSTONE310_FVP OR CONFIG_BOARD_MPS3_CORSTONE310_FVP_NS)
set(SUPPORTED_EMU_PLATFORMS armfvp)
set(ARMFVP_BIN_NAME FVP_Corstone_SSE-310)
if(CONFIG_BOARD_MPS3_CORSTONE310_FVP)
set(ARMFVP_FLAGS
# default is '0x11000000' but should match cpu<i>.INITSVTOR which is 0.
-C mps3_board.sse300.iotss3_systemcontrol.INITSVTOR_RST=0
)
endif()
endif()
board_set_debugger_ifnset(qemu)

8
boards/arm/mps3/board.yml
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@ -14,3 +14,11 @@ board:
- name: 'fvp'
variants:
- name: 'ns'
- name: 'corstone310'
variants:
- name: 'an555'
variants:
- name: 'ns'
- name: 'fvp'
variants:
- name: 'ns'

83
boards/arm/mps3/doc/index.rst
View File

@ -15,12 +15,13 @@ on the MPS3 board. It provides support for the following devices:
- Cortex-M System Design Kit UART
- Ethos-U55 NPU
- AN547 and AN552 support Arm Cortex-M55 CPU
- AN555 support Arm Cortex-M85 CPU
.. image:: img/mps3.jpg
:align: center
:alt: ARM MPS3
`Corstone-300 FVP`_ (Fixed Virtual Platforms) is a complete
`Corstone-300 FVP`_/`Corstone-310 FVP`_ (Fixed Virtual Platforms) is a complete
simulations of the Arm system, including processor, memory and peripherals.
They are available free of charge for Linux and Windows systems.
The FVPs have been selected for simulation since they provide access to the
@ -99,6 +100,9 @@ Zephyr board options
| ``mps3/corstone300/fvp/ns`` | For building Non-Secure firmware |
+-------------------------------+-----------------------------------------------+
FPGA Usage:
- N/A.
FVP Usage:
- To run with the FVP, first set environment variable ``ARMFVP_BIN_PATH`` before using it. Then you can run it with ``west build -t run``.
@ -111,12 +115,69 @@ Zephyr board options
for the Corstone-300 MPS3" from Arm and install it on your host PC. This board
has been tested with version 11.24.13 (Jan 4 2024).
QEMU Usage:
- N/A.
.. tab:: MPS3 Corstone-310 (AN555)
The MPS3+ AN555 is an SoC with Cortex-M85 architecture. Zephyr provides support
for building for both Secure and Non-Secure firmware.
The BOARD options are summarized below:
+-------------------------------+-----------------------------------------------+
| BOARD | Description |
+===============================+===============================================+
| ``mps3/corstone310/an555`` | For building Secure (or Secure-only) firmware |
+-------------------------------+-----------------------------------------------+
| ``mps3/corstone310/an555/ns`` | For building Non-Secure firmware |
+-------------------------------+-----------------------------------------------+
FPGA Usage:
- Follow `Programming and Debugging`_ for build and flash instructions.
FVP Usage:
- FVP not supported for this variant.
QEMU Usage:
- QEMU not supported for this variant of board.
.. tab:: MPS3 Corstone-310 (FVP)
The MPS3+ FVP is an SoC with Cortex-M85 architecture. Zephyr provides support
for building for both Secure and Non-Secure firmware.
The BOARD options are summarized below:
+-------------------------------+-----------------------------------------------+
| BOARD | Description |
+===============================+===============================================+
| ``mps3/corstone310/fvp`` | For building Secure (or Secure-only) firmware |
+-------------------------------+-----------------------------------------------+
| ``mps3/corstone310/fvp/ns`` | For building Non-Secure firmware |
+-------------------------------+-----------------------------------------------+
FPGA Usage:
- N/A.
FVP Usage:
- To run with the FVP, first set environment variable ``ARMFVP_BIN_PATH`` before using it. Then you can run it with ``west build -t run``.
.. code-block:: bash
export ARMFVP_BIN_PATH=/path/to/fvp/directory
west build -b {BOARD qualifier from table above} samples/hello_world -t run
To run the Fixed Virtual Platform simulation tool you must download "FVP model
for the Corstone-310 MPS3" from Arm and install it on your host PC. This board
has been tested with version 11.24.13 (Jan 4 2024).
QEMU Usage:
- N/A.
.. note::
Board qualifier must include the board name as mentioned above.
``mps3/corstone300`` without the board name is not a valid qualifier.
``mps3/corstone300`` or ``mps3/corstone310`` without the board name is not a valid qualifier.
Hardware
********
@ -127,6 +188,8 @@ ARM MPS3 provides the following hardware components:
- AN547 and AN552 support Arm Cortex-M55 CPU and
Soft Macro Model (SMM) implementation of SSE-300 subsystem
- AN555 support Arm Cortex-M85 CPU and
Soft Macro Model (SMM) implementation of SSE-310 subsystem
- Memory
@ -184,6 +247,7 @@ The default configuration can be found in
- For AN547: :zephyr_file:`boards/arm/mps3/mps3_corstone300_an547_defconfig`.
- For AN552: :zephyr_file:`boards/arm/mps3/mps3_corstone300_an552_defconfig`.
- For FVP : :zephyr_file:`boards/arm/mps3/mps3_corstone300_fvp_defconfig`.
- For AN555: :zephyr_file:`boards/arm/mps3/mps3_corstone310_an555_defconfig`.
Serial Port
@ -278,13 +342,19 @@ serial port:
For more details refer to:
- `MPS3 AN547 Technical Reference Manual (TRM)`_
- `MPS3 AN552 Technical Reference Manual (TRM)`_
- `MPS3 AN555 Technical Reference Manual (TRM)`_
- `MPS3 FPGA Prototyping Board Technical Reference Manual (TRM)`_
- `Cortex M55 Generic User Guide`_
- `Cortex M85 Generic User Guide`_
- `Corelink SSE-300 Example Subsystem`_
- `Corelink SSE-310 Example Subsystem`_
.. _Corstone-300 FVP:
https://developer.arm.com/tools-and-software/open-source-software/arm-platforms-software/arm-ecosystem-fvps
.. _Corstone-310 FVP:
https://developer.arm.com/tools-and-software/open-source-software/arm-platforms-software/arm-ecosystem-fvps
.. _MPS3 FPGA Website:
https://developer.arm.com/tools-and-software/development-boards/fpga-prototyping-boards/mps3
@ -294,11 +364,20 @@ For more details refer to:
.. _MPS3 AN552 Technical Reference Manual (TRM):
https://developer.arm.com/documentation/dai0552/latest
.. _MPS3 AN555 Technical Reference Manual (TRM):
https://developer.arm.com/documentation/107642/latest
.. _MPS3 FPGA Prototyping Board Technical Reference Manual (TRM):
https://developer.arm.com/documentation/100765/latest
.. _Cortex M55 Generic User Guide:
https://developer.arm.com/documentation/101051/latest
.. _Cortex M85 Generic User Guide:
https://developer.arm.com/documentation/101924/latest
.. _Corelink SSE-300 Example Subsystem:
https://developer.arm.com/documentation/101772/latest
.. _Corelink SSE-310 Example Subsystem:
https://developer.arm.com/documentation/102778/latest

96
boards/arm/mps3/mps3_corstone310_an555.dts Normal file
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@ -0,0 +1,96 @@
/*
* Copyright 2024 Arm Limited and/or its affiliates <open-source-office@arm.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
/dts-v1/;
#include <arm/armv8.1-m.dtsi>
#include <zephyr/dt-bindings/i2c/i2c.h>
#include <zephyr/dt-bindings/input/input-event-codes.h>
#include <mem.h>
#include "mps3_common.dtsi"
/ {
compatible = "arm,mps3-an555";
#address-cells = <1>;
#size-cells = <1>;
chosen {
zephyr,console = &uart0;
zephyr,shell-uart = &uart0;
zephyr,sram = &dtcm;
zephyr,flash = &itcm;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-m85";
reg = <0>;
#address-cells = <1>;
#size-cells = <1>;
mpu: mpu@e000ed90 {
compatible = "arm,armv8.1m-mpu";
reg = <0xe000ed90 0x40>;
};
};
};
ethosu {
#address-cells = <1>;
#size-cells = <0>;
interrupt-parent = <&nvic>;
ethosu0: ethosu@50004000 {
compatible = "arm,ethos-u";
reg = <0x50004000>;
interrupts = <16 3>;
secure-enable;
privilege-enable;
status = "okay";
};
};
/* We utilize the secure addresses, if you subtract 0x10000000
* you'll get the non-secure alias
*/
itcm: itcm@10000000 { /* alias @ 0x0 */
compatible = "zephyr,memory-region";
reg = <0x10000000 DT_SIZE_K(32)>;
zephyr,memory-region = "ITCM";
};
sram: sram@11000000 { /* alias @ 0x01000000 */
compatible = "zephyr,memory-region", "mmio-sram";
reg = <0x11000000 DT_SIZE_M(2)>;
zephyr,memory-region = "SRAM";
};
dtcm: dtcm@30000000 { /* alias @ 0x20000000 */
compatible = "zephyr,memory-region";
reg = <0x30000000 DT_SIZE_K(32)>;
zephyr,memory-region = "DTCM";
};
isram: sram@31000000 {/* alias @ 0x21000000 */
compatible = "zephyr,memory-region", "mmio-sram";
reg = <0x31000000 DT_SIZE_M(4)>;
zephyr,memory-region = "ISRAM";
};
soc {
peripheral@50000000 {
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x50000000 0x10000000>;
#include "mps3_common_soc_peripheral.dtsi"
};
};
};

22
boards/arm/mps3/mps3_corstone310_an555.yaml Normal file
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@ -0,0 +1,22 @@
# Copyright 2024 Arm Limited and/or its affiliates <open-source-office@arm.com>
# SPDX-License-Identifier: Apache-2.0
identifier: mps3/corstone310/an555
name: Arm MPS3-Corstone310-AN555
type: mcu
arch: arm
ram: 32
flash: 32
toolchain:
- gnuarmemb
- zephyr
- xtools
supported:
- gpio
testing:
ignore_tags:
- drivers
- bluetooth
- net
- timer
vendor: arm

17
boards/arm/mps3/mps3_corstone310_an555_defconfig Normal file
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@ -0,0 +1,17 @@
# Copyright 2024 Arm Limited and/or its affiliates <open-source-office@arm.com>
# SPDX-License-Identifier: Apache-2.0
CONFIG_RUNTIME_NMI=y
CONFIG_ARM_TRUSTZONE_M=y
CONFIG_ARM_MPU=y
# GPIOs
CONFIG_GPIO=y
# Serial
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
CONFIG_SERIAL=y
# Build a Secure firmware image
CONFIG_TRUSTED_EXECUTION_SECURE=y

101
boards/arm/mps3/mps3_corstone310_an555_ns.dts Normal file
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@ -0,0 +1,101 @@
/*
* Copyright 2024 Arm Limited and/or its affiliates <open-source-office@arm.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
/dts-v1/;
#include <arm/armv8.1-m.dtsi>
#include <zephyr/dt-bindings/i2c/i2c.h>
#include <zephyr/dt-bindings/input/input-event-codes.h>
#include <mem.h>
#include "mps3_common.dtsi"
/ {
compatible = "arm,mps3-an555";
#address-cells = <1>;
#size-cells = <1>;
chosen {
zephyr,console = &uart0;
zephyr,shell-uart = &uart0;
zephyr,sram = &ram;
zephyr,flash = &code;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-m85";
reg = <0>;
#address-cells = <1>;
#size-cells = <1>;
mpu: mpu@e000ed90 {
compatible = "arm,armv8.1m-mpu";
reg = <0xe000ed90 0x40>;
};
};
};
/* We utilize the secure addresses, if you subtract 0x10000000
* you'll get the non-secure alias
*/
itcm: itcm@0 {
compatible = "zephyr,memory-region";
reg = <0x0 DT_SIZE_K(32)>;
zephyr,memory-region = "ITCM";
};
sram: sram@1000000 {
compatible = "zephyr,memory-region", "mmio-sram";
reg = <0x1000000 DT_SIZE_M(2)>;
zephyr,memory-region = "SRAM";
};
dtcm: dtcm@20000000 {
compatible = "zephyr,memory-region";
reg = <0x20000000 DT_SIZE_K(512)>;
zephyr,memory-region = "DTCM";
};
isram: sram@21000000 {
compatible = "zephyr,memory-region", "mmio-sram";
reg = <0x21000000 DT_SIZE_M(4)>;
zephyr,memory-region = "ISRAM";
};
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
/* The memory regions defined below must match what the TF-M
* project has defined for that board - a single image boot is
* assumed. Please see the memory layout in:
* https://git.trustedfirmware.org/TF-M/trusted-firmware-m.git/tree/platform/ext/target/mps3/corstone310/common/partition/flash_layout.h
*/
code: memory@1000000 {
reg = <0x01000000 DT_SIZE_M(2)>;
};
ram: memory@21000000 {
reg = <0x21000000 DT_SIZE_M(4)>;
};
};
soc {
peripheral@40000000 {
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x40000000 0x10000000>;
#include "mps3_common_soc_peripheral.dtsi"
};
};
};

17
boards/arm/mps3/mps3_corstone310_an555_ns.yaml Normal file
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@ -0,0 +1,17 @@
# Copyright 2024 Arm Limited and/or its affiliates <open-source-office@arm.com>
# SPDX-License-Identifier: Apache-2.0
identifier: mps3/corstone310/an555/ns
name: Arm MPS3-Corstone310-AN555_ns
type: mcu
arch: arm
ram: 32
flash: 32
toolchain:
- gnuarmemb
- zephyr
- xtools
testing:
default: true
only_tags:
- trusted-firmware-m

18
boards/arm/mps3/mps3_corstone310_an555_ns_defconfig Normal file
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@ -0,0 +1,18 @@
# Copyright 2024 Arm Limited and/or its affiliates <open-source-office@arm.com>
# SPDX-License-Identifier: Apache-2.0
CONFIG_ARM_TRUSTZONE_M=y
CONFIG_RUNTIME_NMI=y
CONFIG_ARM_MPU=y
# GPIOs
CONFIG_GPIO=y
# Serial
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
CONFIG_SERIAL=y
# Build a Non-secure firmware image
CONFIG_TRUSTED_EXECUTION_SECURE=n
CONFIG_TRUSTED_EXECUTION_NONSECURE=y

96
boards/arm/mps3/mps3_corstone310_fvp.dts Normal file
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@ -0,0 +1,96 @@
/*
* Copyright 2024 Arm Limited and/or its affiliates <open-source-office@arm.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
/dts-v1/;
#include <arm/armv8.1-m.dtsi>
#include <zephyr/dt-bindings/i2c/i2c.h>
#include <zephyr/dt-bindings/input/input-event-codes.h>
#include <mem.h>
#include "mps3_common.dtsi"
/ {
compatible = "arm,mps3-fvp";
#address-cells = <1>;
#size-cells = <1>;
chosen {
zephyr,console = &uart0;
zephyr,shell-uart = &uart0;
zephyr,sram = &dtcm;
zephyr,flash = &itcm;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-m85";
reg = <0>;
#address-cells = <1>;
#size-cells = <1>;
mpu: mpu@e000ed90 {
compatible = "arm,armv8.1m-mpu";
reg = <0xe000ed90 0x40>;
};
};
};
ethosu {
#address-cells = <1>;
#size-cells = <0>;
interrupt-parent = <&nvic>;
ethosu0: ethosu@50004000 {
compatible = "arm,ethos-u";
reg = <0x50004000>;
interrupts = <16 3>;
secure-enable;
privilege-enable;
status = "okay";
};
};
/* We utilize the secure addresses, if you subtract 0x10000000
* you'll get the non-secure alias
*/
itcm: itcm@10000000 { /* alias @ 0x0 */
compatible = "zephyr,memory-region";
reg = <0x10000000 DT_SIZE_K(32)>;
zephyr,memory-region = "ITCM";
};
sram: sram@11000000 { /* alias @ 0x01000000 */
compatible = "zephyr,memory-region", "mmio-sram";
reg = <0x11000000 DT_SIZE_M(2)>;
zephyr,memory-region = "SRAM";
};
dtcm: dtcm@30000000 { /* alias @ 0x20000000 */
compatible = "zephyr,memory-region";
reg = <0x30000000 DT_SIZE_K(32)>;
zephyr,memory-region = "DTCM";
};
isram: sram@31000000 {/* alias @ 0x21000000 */
compatible = "zephyr,memory-region", "mmio-sram";
reg = <0x31000000 DT_SIZE_M(4)>;
zephyr,memory-region = "ISRAM";
};
soc {
peripheral@50000000 {
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x50000000 0x10000000>;
#include "mps3_common_soc_peripheral.dtsi"
};
};
};

24
boards/arm/mps3/mps3_corstone310_fvp.yaml Normal file
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@ -0,0 +1,24 @@
# Copyright 2024 Arm Limited and/or its affiliates <open-source-office@arm.com>
# SPDX-License-Identifier: Apache-2.0
identifier: mps3/corstone310/fvp
name: Arm MPS3-Corstone310-FVP
type: mcu
arch: arm
ram: 32
flash: 32
simulation: armfvp
simulation_exec: FVP_Corstone_SSE-310
toolchain:
- gnuarmemb
- zephyr
- xtools
supported:
- gpio
testing:
ignore_tags:
- drivers
- bluetooth
- net
- timer
vendor: arm

17
boards/arm/mps3/mps3_corstone310_fvp_defconfig Normal file
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@ -0,0 +1,17 @@
# Copyright 2024 Arm Limited and/or its affiliates <open-source-office@arm.com>
# SPDX-License-Identifier: Apache-2.0
CONFIG_RUNTIME_NMI=y
CONFIG_ARM_TRUSTZONE_M=y
CONFIG_ARM_MPU=y
# GPIOs
CONFIG_GPIO=y
# Serial
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
CONFIG_SERIAL=y
# Build a Secure firmware image
CONFIG_TRUSTED_EXECUTION_SECURE=y

101
boards/arm/mps3/mps3_corstone310_fvp_ns.dts Normal file
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@ -0,0 +1,101 @@
/*
* Copyright 2024 Arm Limited and/or its affiliates <open-source-office@arm.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
/dts-v1/;
#include <arm/armv8.1-m.dtsi>
#include <zephyr/dt-bindings/i2c/i2c.h>
#include <zephyr/dt-bindings/input/input-event-codes.h>
#include <mem.h>
#include "mps3_common.dtsi"
/ {
compatible = "arm,mps3-fvp";
#address-cells = <1>;
#size-cells = <1>;
chosen {
zephyr,console = &uart0;
zephyr,shell-uart = &uart0;
zephyr,sram = &ram;
zephyr,flash = &code;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-m85";
reg = <0>;
#address-cells = <1>;
#size-cells = <1>;
mpu: mpu@e000ed90 {
compatible = "arm,armv8.1m-mpu";
reg = <0xe000ed90 0x40>;
};
};
};
/* We utilize the secure addresses, if you subtract 0x10000000
* you'll get the non-secure alias
*/
itcm: itcm@0 {
compatible = "zephyr,memory-region";
reg = <0x0 DT_SIZE_K(32)>;
zephyr,memory-region = "ITCM";
};
sram: sram@1000000 {
compatible = "zephyr,memory-region", "mmio-sram";
reg = <0x1000000 DT_SIZE_M(2)>;
zephyr,memory-region = "SRAM";
};
dtcm: dtcm@20000000 {
compatible = "zephyr,memory-region";
reg = <0x20000000 DT_SIZE_K(512)>;
zephyr,memory-region = "DTCM";
};
isram: sram@21000000 {
compatible = "zephyr,memory-region", "mmio-sram";
reg = <0x21000000 DT_SIZE_M(4)>;
zephyr,memory-region = "ISRAM";
};
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
/* The memory regions defined below must match what the TF-M
* project has defined for that board - a single image boot is
* assumed. Please see the memory layout in:
* https://git.trustedfirmware.org/TF-M/trusted-firmware-m.git/tree/platform/ext/target/mps3/corstone310/common/partition/flash_layout.h
*/
code: memory@28080000 {
reg = <0x28080000 DT_SIZE_K(512)>;
};
ram: memory@21020000 {
reg = <0x21020000 DT_SIZE_M(1)>;
};
};
soc {
peripheral@40000000 {
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x40000000 0x10000000>;
#include "mps3_common_soc_peripheral.dtsi"
};
};
};

17
boards/arm/mps3/mps3_corstone310_fvp_ns.yaml Normal file
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@ -0,0 +1,17 @@
# Copyright 2024 Arm Limited and/or its affiliates <open-source-office@arm.com>
# SPDX-License-Identifier: Apache-2.0
identifier: mps3/corstone310/fvp/ns
name: Arm MPS3-Corstone310-FVP_ns
type: mcu
arch: arm
ram: 32
flash: 32
toolchain:
- gnuarmemb
- zephyr
- xtools
testing:
default: true
only_tags:
- trusted-firmware-m

19
boards/arm/mps3/mps3_corstone310_fvp_ns_defconfig Normal file
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@ -0,0 +1,19 @@
# Copyright 2024 Arm Limited and/or its affiliates <open-source-office@arm.com>
# SPDX-License-Identifier: Apache-2.0
CONFIG_ARM_TRUSTZONE_M=y
CONFIG_RUNTIME_NMI=y
CONFIG_ARM_MPU=y
# GPIOs
CONFIG_GPIO=y
# Serial
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
CONFIG_SERIAL=y
# Build a Non-secure firmware image
CONFIG_TRUSTED_EXECUTION_SECURE=n
CONFIG_TRUSTED_EXECUTION_NONSECURE=y
CONFIG_BUILD_WITH_TFM=y

2
modules/trusted-firmware-m/Kconfig.tfm
View File

@ -15,6 +15,8 @@ config TFM_BOARD
default "arm/mps3/corstone300/fvp" if BOARD_MPS3_CORSTONE300_FVP_NS
default "arm/mps3/corstone300/an547" if BOARD_MPS3_CORSTONE300_AN547_NS
default "arm/mps3/corstone300/an552" if BOARD_MPS3_CORSTONE300_AN552_NS
default "arm/mps3/corstone310/an555" if BOARD_MPS3_CORSTONE310_AN555_NS
default "arm/mps3/corstone310/fvp" if BOARD_MPS3_CORSTONE310_FVP_NS
default "stm/b_u585i_iot02a" if BOARD_B_U585I_IOT02A
default "stm/nucleo_l552ze_q" if BOARD_NUCLEO_L552ZE_Q
default "stm/stm32l562e_dk" if BOARD_STM32L562E_DK

11
soc/arm/mps3/Kconfig
View File

@ -16,6 +16,17 @@ config SOC_MPS3_CORSTONE300
select ARMV8_1_M_MVEF
select ARMV8_1_M_PMU
config SOC_MPS3_CORSTONE310
select CPU_CORTEX_M85
select CPU_HAS_ARM_SAU
select CPU_HAS_ARM_MPU
select CPU_HAS_FPU
select ARMV8_M_DSP
select ARMV8_1_M_MVEI
select ARMV8_1_M_MVEF
select ARMV8_1_M_PMU
config ARMV8_1_M_PMU_EVENTCNT
int
default 8 if SOC_MPS3_CORSTONE300
default 8 if SOC_MPS3_CORSTONE310

9
soc/arm/mps3/Kconfig.defconfig.mps3_corstone310 Normal file
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@ -0,0 +1,9 @@
# Copyright 2024 Arm Limited and/or its affiliates <open-source-office@arm.com>
# SPDX-License-Identifier: Apache-2.0
if SOC_MPS3_CORSTONE310
config NUM_IRQS
default 128
endif

5
soc/arm/mps3/Kconfig.soc
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@ -15,5 +15,10 @@ config SOC_MPS3_CORSTONE300
bool
select SOC_SERIES_MPS3
config SOC_MPS3_CORSTONE310
bool
select SOC_SERIES_MPS3
config SOC
default "corstone300" if SOC_MPS3_CORSTONE300
default "corstone310" if SOC_MPS3_CORSTONE310

1
soc/arm/soc.yml
View File

@ -11,6 +11,7 @@ family:
- name: mps3
socs:
- name: corstone300
- name: corstone310
- name: musca
socs:
- name: musca_b1