riscv: make arch_is_user_context() SMP compatible
This is painful. There is no way for u-mode code to know if we're currently executing in u-mode without generating a fault, besides stealing a general purpose register away from the standard ABI that is. And a global variable doesn't work on SMP as this must be per-CPU and we could be migrated to another CPU just at the right moment to peek at the wrong CPU variable (and u-mode can't disable preemption either). So, given that we'll have to pay the price of an exception entry anyway, let's at least make it free to privileged threads by using the mscratch register as the non-user context indicator (it must be zero in m-mode for exception entry to work properly). In the case of u-mode we'll simulate a proper return value in the exception trap code. Let's settle on the return value in t0 and omit the volatile to give the compiler a chance to cache the result. Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
This commit is contained in:
Nicolas Pitre
Anas Nashif
parent
af2d875c5d
commit
c8bfc2afda
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@ -41,10 +41,11 @@
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op fa6, __z_arch_esf_t_fa6_OFFSET(reg) ;\
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op fa7, __z_arch_esf_t_fa7_OFFSET(reg) ;
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#define DO_CALLER_SAVED(op) \
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op ra, __z_arch_esf_t_ra_OFFSET(sp) ;\
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#define DO_CALLER_SAVED_T0T1(op) \
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op t0, __z_arch_esf_t_t0_OFFSET(sp) ;\
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op t1, __z_arch_esf_t_t1_OFFSET(sp) ;\
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op t1, __z_arch_esf_t_t1_OFFSET(sp)
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#define DO_CALLER_SAVED_REST(op) \
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op t2, __z_arch_esf_t_t2_OFFSET(sp) ;\
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op t3, __z_arch_esf_t_t3_OFFSET(sp) ;\
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op t4, __z_arch_esf_t_t4_OFFSET(sp) ;\
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@ -57,7 +58,8 @@
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op a4, __z_arch_esf_t_a4_OFFSET(sp) ;\
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op a5, __z_arch_esf_t_a5_OFFSET(sp) ;\
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op a6, __z_arch_esf_t_a6_OFFSET(sp) ;\
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op a7, __z_arch_esf_t_a7_OFFSET(sp) ;
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op a7, __z_arch_esf_t_a7_OFFSET(sp) ;\
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op ra, __z_arch_esf_t_ra_OFFSET(sp)
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#ifdef CONFIG_SMP
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#define GET_CURRENT_CPU(dst, tmp) \
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@ -138,12 +140,46 @@ SECTION_FUNC(exception.entry, __irq_wrapper)
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/* restore privileged stack pointer and zero the scratch reg */
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csrrw sp, mscratch, sp
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#ifdef CONFIG_SMP
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j 2f
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1: /*
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* We were in user space. Determine if it attempted to execute an
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* arch_is_user_context() based on mscratch access. We want to return
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* to u-mode with t0!=0 as quickly as possible if so.
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*/
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addi sp, sp, -__z_arch_esf_t_SIZEOF
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DO_CALLER_SAVED_T0T1(sr) ;
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/* First, determine if we had an illegal instruction exception. */
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csrr t0, mcause
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li t1, SOC_MCAUSE_EXP_MASK
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and t0, t0, t1
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addi t0, t0, -2 /* = 2 = illegal instruction */
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bnez t0, 3f
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/* Make sure it was actually a "csrr t0, mscratch" */
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csrr t0, mepc
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lw t0, 0(t0)
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li t1, 0x340022f3
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bne t0, t1, 3f
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/* So it was: skip over it and return leaving t0 clobbered. */
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csrr t0, mepc
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addi t0, t0, 4
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csrw mepc, t0
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lr t1, __z_arch_esf_t_t1_OFFSET(sp)
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addi sp, sp, __z_arch_esf_t_SIZEOF
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/* restore user stack pointer and leave */
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csrrw sp, mscratch, sp
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mret
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2:
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#endif /* CONFIG_SMP */
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1:
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#endif
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#endif /* CONFIG_USERSPACE */
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/* Save caller-saved registers on current thread stack. */
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addi sp, sp, -__z_arch_esf_t_SIZEOF
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DO_CALLER_SAVED(sr) ;
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DO_CALLER_SAVED_T0T1(sr) ;
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3: DO_CALLER_SAVED_REST(sr) ;
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/* Save s0 in the esf and load it with &_current_cpu. */
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sr s0, __z_arch_esf_t_s0_OFFSET(sp)
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@ -164,9 +200,11 @@ SECTION_FUNC(exception.entry, __irq_wrapper)
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/* save stack value to be restored later */
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sr t0, __z_arch_esf_t_sp_OFFSET(sp)
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#if !defined(CONFIG_SMP)
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/* Clear user mode variable */
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la t0, is_user_mode
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sw zero, 0(t0)
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#endif
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#endif
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/* Save MEPC register */
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@ -508,10 +546,12 @@ no_fp: /* make sure this is reflected in the restored mstatus */
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and t0, t4, t1
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bnez t0, 1f
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#if !defined(CONFIG_SMP)
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/* Set user mode variable */
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li t0, 1
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la t1, is_user_mode
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sw t0, 0(t1)
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#endif
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/* load scratch reg with stack pointer for next exception entry */
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add t0, sp, __z_arch_esf_t_SIZEOF
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@ -523,7 +563,8 @@ no_fp: /* make sure this is reflected in the restored mstatus */
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lr s0, __z_arch_esf_t_s0_OFFSET(sp)
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/* Restore caller-saved registers from thread stack */
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DO_CALLER_SAVED(lr)
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DO_CALLER_SAVED_T0T1(lr)
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DO_CALLER_SAVED_REST(lr)
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#ifdef CONFIG_USERSPACE
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/* retrieve saved stack pointer */
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@ -67,7 +67,7 @@ struct riscv_pmp_region {
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enum pmp_region_mode mode;
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};
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#ifdef CONFIG_USERSPACE
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#if defined(CONFIG_USERSPACE) && !defined(CONFIG_SMP)
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extern uint32_t is_user_mode;
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#endif
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@ -635,6 +635,7 @@ void z_riscv_pmp_clear_config(void)
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void z_riscv_init_user_accesses(struct k_thread *thread)
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{
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struct riscv_pmp_region dynamic_regions[] = {
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#if !defined(CONFIG_SMP)
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{
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/* MCU state */
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.start = (ulong_t) &is_user_mode,
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@ -642,6 +643,7 @@ void z_riscv_init_user_accesses(struct k_thread *thread)
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.perm = PMP_R,
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.mode = PMP_MODE_NA4,
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},
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#endif
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{
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/* User-mode thread stack */
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.start = thread->stack_info.start,
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@ -11,7 +11,7 @@
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#include <stdio.h>
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#include <core_pmp.h>
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#ifdef CONFIG_USERSPACE
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#if defined(CONFIG_USERSPACE) && !defined(CONFIG_SMP)
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/*
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* Glogal variable used to know the current mode running.
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* Is not boolean because it must match the PMP granularity of the arch.
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@ -251,7 +251,9 @@ FUNC_NORETURN void arch_user_mode_enter(k_thread_entry_t user_entry,
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z_riscv_init_user_accesses(_current);
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z_riscv_configure_user_allowed_stack(_current);
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#if !defined(CONFIG_SMP)
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is_user_mode = true;
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#endif
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register void *a0 __asm__("a0") = user_entry;
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register void *a1 __asm__("a1") = p1;
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@ -149,9 +149,33 @@ static inline uintptr_t arch_syscall_invoke0(uintptr_t call_id)
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#ifdef CONFIG_USERSPACE
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static inline bool arch_is_user_context(void)
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{
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#ifdef CONFIG_SMP
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/*
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* This is painful. There is no way for u-mode code to know if we're
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* currently executing in u-mode without generating a fault, besides
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* stealing a general purpose register away from the standard ABI
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* that is. And a global variable doesn't work on SMP as this must be
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* per-CPU and we could be migrated to another CPU just at the right
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* moment to peek at the wrong CPU variable (and u-mode can't disable
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* preemption either).
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*
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* So, given that we'll have to pay the price of an exception entry
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* anyway, let's at least make it free to privileged threads by using
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* the mscratch register as the non-user context indicator (it must
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* be zero in m-mode for exception entry to work properly). In the
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* case of u-mode we'll simulate a proper return value in the
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* exception trap code. Let's settle on the return value in t0
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* and omit the volatile to give the compiler a chance to cache
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* the result.
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*/
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register ulong_t is_user __asm__ ("t0");
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__asm__ ("csrr %0, mscratch" : "=r" (is_user));
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return is_user != 0;
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#else
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/* Defined in arch/riscv/core/thread.c */
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extern uint32_t is_user_mode;
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return is_user_mode;
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#endif
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}
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#endif
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