boards: silabs: Remove clock configuration
Clock setup is now done by the clock manager based on device tree configuration. Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
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955aca6c09
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c6c3e194d9
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@ -8,22 +8,12 @@
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#include <zephyr/init.h>
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#include <zephyr/logging/log.h>
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#ifdef CONFIG_SOC_GECKO_DEV_INIT
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#include "em_cmu.h"
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#endif
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LOG_MODULE_REGISTER(thunderboard, CONFIG_BOARD_SLTB010A_LOG_LEVEL);
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static int thunderboard_init_clocks(void);
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static int thunderboard_init(void)
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{
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int ret;
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#ifdef CONFIG_SOC_GECKO_DEV_INIT
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thunderboard_init_clocks();
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#endif
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static struct gpio_dt_spec wake_up_gpio_dev =
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GPIO_DT_SPEC_GET(DT_NODELABEL(wake_up_trigger), gpios);
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@ -40,25 +30,5 @@ static int thunderboard_init(void)
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return 0;
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}
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#ifdef CONFIG_SOC_GECKO_DEV_INIT
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static int thunderboard_init_clocks(void)
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{
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CMU_ClockSelectSet(cmuClock_SYSCLK, cmuSelect_HFRCODPLL);
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#if defined(_CMU_EM01GRPACLKCTRL_MASK)
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CMU_ClockSelectSet(cmuClock_EM01GRPACLK, cmuSelect_HFRCODPLL);
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#endif
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#if defined(_CMU_EM01GRPBCLKCTRL_MASK)
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CMU_ClockSelectSet(cmuClock_EM01GRPBCLK, cmuSelect_HFRCODPLL);
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#endif
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CMU_ClockSelectSet(cmuClock_EM23GRPACLK, cmuSelect_LFRCO);
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#if defined(RTCC_PRESENT)
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CMU_ClockSelectSet(cmuClock_RTCC, cmuSelect_LFRCO);
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#endif
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CMU_ClockSelectSet(cmuClock_WDOG0, cmuSelect_LFRCO);
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return 0;
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}
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#endif
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/* needs to be done after GPIO driver init */
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SYS_INIT(thunderboard_init, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE);
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@ -9,21 +9,12 @@
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#include <zephyr/sys/printk.h>
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#include <zephyr/logging/log.h>
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#ifdef CONFIG_SOC_GECKO_DEV_INIT
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#include "em_cmu.h"
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#endif
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LOG_MODULE_REGISTER(efr32xg24_dk2601b, CONFIG_BOARD_EFR32MG24_LOG_LEVEL);
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static int efr32xg24_dk2601b_init_clocks(void);
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static int efr32xg24_dk2601b_init(void)
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{
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int ret;
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#ifdef CONFIG_SOC_GECKO_DEV_INIT
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efr32xg24_dk2601b_init_clocks();
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#endif
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static struct gpio_dt_spec wake_up_gpio_dev =
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GPIO_DT_SPEC_GET(DT_NODELABEL(wake_up_trigger), gpios);
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@ -40,32 +31,5 @@ static int efr32xg24_dk2601b_init(void)
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return 0;
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}
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#ifdef CONFIG_SOC_GECKO_DEV_INIT
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static int efr32xg24_dk2601b_init_clocks(void)
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{
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CMU_ClockSelectSet(cmuClock_SYSCLK, cmuSelect_HFRCODPLL);
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#if defined(_CMU_EM01GRPACLKCTRL_MASK)
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CMU_ClockSelectSet(cmuClock_EM01GRPACLK, cmuSelect_HFRCODPLL);
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#endif
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#if defined(_CMU_EM01GRPBCLKCTRL_MASK)
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CMU_ClockSelectSet(cmuClock_EM01GRPBCLK, cmuSelect_HFRCODPLL);
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#endif
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CMU_ClockSelectSet(cmuClock_EM23GRPACLK, cmuSelect_LFRCO);
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CMU_ClockSelectSet(cmuClock_EM4GRPACLK, cmuSelect_LFRCO);
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#if defined(RTCC_PRESENT)
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CMU_ClockSelectSet(cmuClock_RTCC, cmuSelect_LFRCO);
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#endif
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#if defined(SYSRTC_PRESENT)
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CMU_ClockSelectSet(cmuClock_SYSRTC, cmuSelect_LFRCO);
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#endif
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CMU_ClockSelectSet(cmuClock_WDOG0, cmuSelect_LFRCO);
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#if WDOG_COUNT > 1
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CMU_ClockSelectSet(cmuClock_WDOG1, cmuSelect_LFRCO);
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#endif
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return 0;
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}
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#endif
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/* needs to be done after GPIO driver init */
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SYS_INIT(efr32xg24_dk2601b_init, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE);
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@ -7,8 +7,6 @@ CONFIG_UART_CONSOLE=y
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CONFIG_SERIAL=y
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CONFIG_CORTEX_M_SYSTICK=y
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CONFIG_GPIO=y
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CONFIG_CMU_HFCLK_HFXO=y
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CONFIG_CMU_HFCLK_LFXO=y
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CONFIG_HW_STACK_PROTECTION=y
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CONFIG_PINCTRL=y
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CONFIG_REGULATOR=y
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@ -8,22 +8,12 @@
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#include <zephyr/init.h>
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#include <zephyr/logging/log.h>
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#ifdef CONFIG_SOC_GECKO_DEV_INIT
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#include "em_cmu.h"
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#endif
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LOG_MODULE_REGISTER(dev_kit, CONFIG_BOARD_XG27_DK2602A_LOG_LEVEL);
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static int dev_kit_init_clocks(void);
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static int dev_kit_init(void)
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{
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int ret;
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#ifdef CONFIG_SOC_GECKO_DEV_INIT
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dev_kit_init_clocks();
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#endif
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static struct gpio_dt_spec wake_up_gpio_dev =
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GPIO_DT_SPEC_GET(DT_NODELABEL(wake_up_trigger), gpios);
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@ -40,25 +30,5 @@ static int dev_kit_init(void)
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return 0;
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}
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#ifdef CONFIG_SOC_GECKO_DEV_INIT
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static int dev_kit_init_clocks(void)
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{
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CMU_ClockSelectSet(cmuClock_SYSCLK, cmuSelect_HFRCODPLL);
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#if defined(_CMU_EM01GRPACLKCTRL_MASK)
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CMU_ClockSelectSet(cmuClock_EM01GRPACLK, cmuSelect_HFRCODPLL);
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#endif
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#if defined(_CMU_EM01GRPBCLKCTRL_MASK)
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CMU_ClockSelectSet(cmuClock_EM01GRPBCLK, cmuSelect_HFRCODPLL);
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#endif
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CMU_ClockSelectSet(cmuClock_EM23GRPACLK, cmuSelect_LFRCO);
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#if defined(RTCC_PRESENT)
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CMU_ClockSelectSet(cmuClock_RTCC, cmuSelect_LFRCO);
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#endif
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CMU_ClockSelectSet(cmuClock_WDOG0, cmuSelect_LFRCO);
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return 0;
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}
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#endif
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/* needs to be done after GPIO driver init */
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SYS_INIT(dev_kit_init, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE);
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@ -10,22 +10,13 @@
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#include <zephyr/sys/printk.h>
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#include <zephyr/logging/log.h>
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#ifdef CONFIG_SOC_GECKO_DEV_INIT
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#include "em_cmu.h"
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#endif
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LOG_MODULE_REGISTER(sparkfun_thing_plus_mgm240p,
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CONFIG_BOARD_SPARKFUN_THING_PLUS_MATTER_MGM240P_LOG_LEVEL);
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static int sparkfun_thing_plus_mgm240p_init_clocks(void);
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static int sparkfun_thing_plus_mgm240p_init(void)
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{
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int ret;
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#ifdef CONFIG_SOC_GECKO_DEV_INIT
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sparkfun_thing_plus_mgm240p_init_clocks();
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#endif
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static struct gpio_dt_spec wake_up_gpio_dev =
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GPIO_DT_SPEC_GET(DT_NODELABEL(wake_up_trigger), gpios);
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@ -42,35 +33,5 @@ static int sparkfun_thing_plus_mgm240p_init(void)
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return 0;
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}
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#ifdef CONFIG_SOC_GECKO_DEV_INIT
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static int sparkfun_thing_plus_mgm240p_init_clocks(void)
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{
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CMU_ClockSelectSet(cmuClock_SYSCLK, cmuSelect_HFRCODPLL);
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#if defined(_CMU_EM01GRPACLKCTRL_MASK)
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CMU_ClockSelectSet(cmuClock_EM01GRPACLK, cmuSelect_HFRCODPLL);
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#endif
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#if defined(_CMU_EM01GRPBCLKCTRL_MASK)
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CMU_ClockSelectSet(cmuClock_EM01GRPBCLK, cmuSelect_HFRCODPLL);
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#endif
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#if defined(_CMU_EM01GRPCCLKCTRL_MASK)
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CMU_ClockSelectSet(cmuClock_EM01GRPCCLK, cmuSelect_HFRCODPLL);
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#endif
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CMU_ClockSelectSet(cmuClock_EM23GRPACLK, cmuSelect_LFRCO);
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CMU_ClockSelectSet(cmuClock_EM4GRPACLK, cmuSelect_LFRCO);
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#if defined(RTCC_PRESENT)
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CMU_ClockSelectSet(cmuClock_RTCC, cmuSelect_LFRCO);
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#endif
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#if defined(SYSRTC_PRESENT)
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CMU_ClockSelectSet(cmuClock_SYSRTC, cmuSelect_LFRCO);
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#endif
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CMU_ClockSelectSet(cmuClock_WDOG0, cmuSelect_LFRCO);
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#if WDOG_COUNT > 1
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CMU_ClockSelectSet(cmuClock_WDOG1, cmuSelect_LFRCO);
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#endif
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return 0;
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}
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#endif
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/* needs to be done after GPIO driver init */
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SYS_INIT(sparkfun_thing_plus_mgm240p_init, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE);
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@ -9,10 +9,8 @@ CONFIG_SERIAL=y
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CONFIG_CORTEX_M_SYSTICK=y
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CONFIG_GPIO=y
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CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=76800000
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CONFIG_CMU_HFCLK_HFXO=y
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CONFIG_SOC_GECKO_EMU_DCDC=y
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CONFIG_SOC_GECKO_EMU_DCDC_MODE_ON=y
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CONFIG_CMU_HFCLK_LFXO=y
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CONFIG_HW_STACK_PROTECTION=y
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CONFIG_PINCTRL=y
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CONFIG_REGULATOR=y
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