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drivers: ethernet: phy_realtek_rtl8211f: enable RGMII TX/RX delay 

The RGMII specifies output TXC/RXC and TXD/RXD without any clock skew.
Need to add skew on clock line to make sure the other side sample
right data. This can also be done in PCB traces.
This patch is to enable RGMII TX/RX delay to ensure timing.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
This commit is contained in:
Yangbo Lu 2024-06-11 15:09:48 +09:00 committed by Alberto Escolar
parent e5f6cee9fb
commit b77dab6199
1 changed files with 47 additions and 2 deletions
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49
drivers/ethernet/phy/phy_realtek_rtl8211f.c
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@ -39,6 +39,12 @@ LOG_MODULE_REGISTER(LOG_MODULE_NAME);
#define PHY_RT_RTL8211F_PAGSR_REG (0x1F)
#define PHY_RT_RTL8211F_PAGE_MIICR_ADDR (0xD08)
#define PHY_RT_RTL8211F_MIICR1_REG (0x11)
#define PHY_RT_RTL8211F_MIICR2_REG (0x15)
#define PHY_RT_RTL8211F_MIICR1_TXDLY_MASK BIT(8)
#define PHY_RT_RTL8211F_MIICR2_RXDLY_MASK BIT(3)
#define PHY_RT_RTL8211F_PAGE_INTR_PIN_ADDR (0xD40)
#define PHY_RT_RTL8211F_INTR_PIN_REG (0x16)
#define PHY_RT_RTL8211F_INTR_PIN_MASK BIT(5)
@ -475,9 +481,7 @@ static int phy_rt_rtl8211f_init(const struct device *dev)
{
const struct rt_rtl8211f_config *config = dev->config;
struct rt_rtl8211f_data *data = dev->data;
#if DT_ANY_INST_HAS_PROP_STATUS_OKAY(int_gpios)
uint32_t reg_val;
#endif /* DT_ANY_INST_HAS_PROP_STATUS_OKAY(int_gpios) */
int ret;
data->dev = dev;
@ -506,6 +510,47 @@ static int phy_rt_rtl8211f_init(const struct device *dev)
return ret;
}
/* Set RGMII Tx/Rx Delay. */
ret = phy_rt_rtl8211f_write(dev, PHY_RT_RTL8211F_PAGSR_REG,
PHY_RT_RTL8211F_PAGE_MIICR_ADDR);
if (ret) {
LOG_ERR("Error writing phy (%d) page select register", config->addr);
return ret;
}
ret = phy_rt_rtl8211f_read(dev, PHY_RT_RTL8211F_MIICR1_REG, &reg_val);
if (ret) {
LOG_ERR("Error reading phy (%d) mii control register1", config->addr);
return ret;
}
reg_val |= PHY_RT_RTL8211F_MIICR1_TXDLY_MASK;
ret = phy_rt_rtl8211f_write(dev, PHY_RT_RTL8211F_MIICR1_REG, reg_val);
if (ret) {
LOG_ERR("Error writing phy (%d) mii control register1", config->addr);
return ret;
}
ret = phy_rt_rtl8211f_read(dev, PHY_RT_RTL8211F_MIICR2_REG, &reg_val);
if (ret) {
LOG_ERR("Error reading phy (%d) mii control register2", config->addr);
return ret;
}
reg_val |= PHY_RT_RTL8211F_MIICR2_RXDLY_MASK;
ret = phy_rt_rtl8211f_write(dev, PHY_RT_RTL8211F_MIICR2_REG, reg_val);
if (ret) {
LOG_ERR("Error writing phy (%d) mii control register2", config->addr);
return ret;
}
/* Restore to default page 0 */
ret = phy_rt_rtl8211f_write(dev, PHY_RT_RTL8211F_PAGSR_REG, 0);
if (ret) {
LOG_ERR("Error writing phy (%d) page select register", config->addr);
return ret;
}
k_work_init_delayable(&data->phy_monitor_work, phy_rt_rtl8211f_monitor_work_handler);
#if DT_ANY_INST_HAS_PROP_STATUS_OKAY(int_gpios)