From b26d21fcfdd6713d80a323b794adf0a29fa06361 Mon Sep 17 00:00:00 2001 From: Laurentiu Mihalcea Date: Wed, 14 Aug 2024 16:19:36 +0300 Subject: [PATCH] drivers: dma: dma_nxp_edma: support 64-bit TCD On some EDMA versions, some TCD registers (e.g: SADDR, DADDR, SLAST, DLAST, etc...) are extended to 64 bits via adding a new HIGH register holding the value of bits [63:32]. Since, for now, the driver doesn't support 64-bit addresses, this scenario is supported by sign-extending the 32-bit value written to SLAST/DLAST. SADDR and DADDR are taken care of on HAL side. Signed-off-by: Laurentiu Mihalcea --- drivers/dma/dma_nxp_edma.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/dma/dma_nxp_edma.h b/drivers/dma/dma_nxp_edma.h index c96630a7186..ca345ad3fbe 100644 --- a/drivers/dma/dma_nxp_edma.h +++ b/drivers/dma/dma_nxp_edma.h @@ -514,6 +514,13 @@ static inline int set_slast_dlast(struct dma_config *dma_cfg, EDMA_ChannelRegWrite(data->hal_cfg, chan_id, EDMA_TCD_SLAST_SDA, slast); EDMA_ChannelRegWrite(data->hal_cfg, chan_id, EDMA_TCD_DLAST_SGA, dlast); + if (data->hal_cfg->flags & EDMA_HAS_64BIT_TCD_FLAG) { + EDMA_ChannelRegWrite(data->hal_cfg, chan_id, EDMA_TCD_SLAST_SDA_HIGH, + slast >= 0x0 ? 0x0 : 0xffffffff); + EDMA_ChannelRegWrite(data->hal_cfg, chan_id, EDMA_TCD_DLAST_SGA_HIGH, + dlast >= 0x0 ? 0x0 : 0xffffffff); + } + return 0; }