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coding guidelines: comply with MISRA C:2012 Rule 7.2 

MISRA C:2012 Rule 7.2 (A `u' or `U' suffix shall be applied to all
integer constants that are represented in an unsigned type)

Added missing `U' suffixes in constants that are involved in the
analyzed build, plus a few more not to introduce inconsistencies
with respect to nearby constants that are either unused in the
build (but implicitly unsigned) or are used and are immediately
converted to unsigned.

Signed-off-by: Abramo Bagnara <abramo.bagnara@bugseng.com>
This commit is contained in:
Abramo Bagnara 2021-11-12 16:45:12 +01:00 committed by Anas Nashif
parent e68913567d
commit ada9ca4c93
4 changed files with 18 additions and 18 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
drivers/pcie/host/pcie.c
View File

@ -85,7 +85,7 @@ uint32_t pcie_get_ext_cap(pcie_bdf_t bdf, uint32_t cap_id)
while (reg) {
data = pcie_conf_read(bdf, reg);
if (!data || data == 0xffffffff) {
if (!data || data == 0xffffffffU) {
return 0;
}
@ -139,7 +139,7 @@ bool pcie_get_mbar(pcie_bdf_t bdf,
return false;
}
pcie_conf_write(bdf, reg, 0xFFFFFFFF);
pcie_conf_write(bdf, reg, 0xFFFFFFFFU);
size = pcie_conf_read(bdf, reg);
pcie_conf_write(bdf, reg, (uint32_t)phys_addr);
@ -153,7 +153,7 @@ bool pcie_get_mbar(pcie_bdf_t bdf,
return false;
}
pcie_conf_write(bdf, reg, 0xFFFFFFFF);
pcie_conf_write(bdf, reg, 0xFFFFFFFFU);
size |= ((uint64_t)pcie_conf_read(bdf, reg)) << 32;
pcie_conf_write(bdf, reg, (uint32_t)((uint64_t)phys_addr >> 32));
} else if (PCIE_CONF_BAR_ADDR(phys_addr) == PCIE_CONF_BAR_INVAL ||

16
include/zephyr/arch/x86/msr.h
View File

@ -24,7 +24,7 @@
#define X86_X2APIC_BASE_MSR 0x00000800 /* .. thru 0x00000BFF */
#define X86_EFER_MSR 0xC0000080
#define X86_EFER_MSR 0xC0000080U
#define X86_EFER_MSR_SCE BIT(0)
#define X86_EFER_MSR_LME BIT(8)
#define X86_EFER_MSR_NXE BIT(11)
@ -33,17 +33,17 @@
* 47:32 Kernel CS (SS = CS+8)
* 63:48 User CS (SS = CS+8)
*/
#define X86_STAR_MSR 0xC0000081
#define X86_STAR_MSR 0xC0000081U
/* Location for system call entry point */
#define X86_LSTAR_MSR 0xC0000082
#define X86_LSTAR_MSR 0xC0000082U
/* Low 32 bits in this MSR are the SYSCALL mask applied to EFLAGS */
#define X86_FMASK_MSR 0xC0000084
#define X86_FMASK_MSR 0xC0000084U
#define X86_FS_BASE 0xC0000100
#define X86_GS_BASE 0xC0000101
#define X86_KERNEL_GS_BASE 0xC0000102
#define X86_FS_BASE 0xC0000100U
#define X86_GS_BASE 0xC0000101U
#define X86_KERNEL_GS_BASE 0xC0000102U
#ifndef _ASMLANGUAGE
#ifdef __cplusplus
@ -58,7 +58,7 @@ extern "C" {
static inline void z_x86_msr_write(unsigned int msr, uint64_t data)
{
uint32_t high = data >> 32;
uint32_t low = data & 0xFFFFFFFF;
uint32_t low = data & 0xFFFFFFFFU;
__asm__ volatile ("wrmsr" : : "c"(msr), "a"(low), "d"(high));
}

6
include/zephyr/drivers/pcie/pcie.h
View File

@ -370,9 +370,9 @@ extern bool pcie_connect_dynamic_irq(pcie_bdf_t bdf,
#define PCIE_CONF_INTR_IRQ(w) ((w) & 0xFFU)
#define PCIE_CONF_INTR_IRQ_NONE 0xFFU /* no interrupt routed */
#define PCIE_MAX_BUS (0xFFFFFFFF & PCIE_BDF_BUS_MASK)
#define PCIE_MAX_DEV (0xFFFFFFFF & PCIE_BDF_DEV_MASK)
#define PCIE_MAX_FUNC (0xFFFFFFFF & PCIE_BDF_FUNC_MASK)
#define PCIE_MAX_BUS (0xFFFFFFFFU & PCIE_BDF_BUS_MASK)
#define PCIE_MAX_DEV (0xFFFFFFFFU & PCIE_BDF_DEV_MASK)
#define PCIE_MAX_FUNC (0xFFFFFFFFU & PCIE_BDF_FUNC_MASK)
/**
* @brief Initialize an interrupt handler for a PCIe endpoint IRQ

8
lib/os/crc32_sw.c
View File

@ -15,10 +15,10 @@ uint32_t crc32_ieee_update(uint32_t crc, const uint8_t *data, size_t len)
{
/* crc table generated from polynomial 0xedb88320 */
static const uint32_t table[16] = {
0x00000000, 0x1db71064, 0x3b6e20c8, 0x26d930ac,
0x76dc4190, 0x6b6b51f4, 0x4db26158, 0x5005713c,
0xedb88320, 0xf00f9344, 0xd6d6a3e8, 0xcb61b38c,
0x9b64c2b0, 0x86d3d2d4, 0xa00ae278, 0xbdbdf21c,
0x00000000U, 0x1db71064U, 0x3b6e20c8U, 0x26d930acU,
0x76dc4190U, 0x6b6b51f4U, 0x4db26158U, 0x5005713cU,
0xedb88320U, 0xf00f9344U, 0xd6d6a3e8U, 0xcb61b38cU,
0x9b64c2b0U, 0x86d3d2d4U, 0xa00ae278U, 0xbdbdf21cU,
};
crc = ~crc;