From a9543e0ff4a79930d256d5a0eedf72214bea061e Mon Sep 17 00:00:00 2001
From: Filip Kokosinski <fkokosinski@antmicro.com>
Date: Tue, 22 Mar 2022 09:21:59 +0100
Subject: [PATCH] boards: qemu_riscv32: add pinctrl configuration for
 qemu_riscv32_xip

Add pinctrl configuration for future use with the new pinctrl driver.

Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
---
 .../qemu_riscv32/qemu_riscv32_xip-pinctrl.dtsi  | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)
 create mode 100644 boards/riscv/qemu_riscv32/qemu_riscv32_xip-pinctrl.dtsi

diff --git a/boards/riscv/qemu_riscv32/qemu_riscv32_xip-pinctrl.dtsi b/boards/riscv/qemu_riscv32/qemu_riscv32_xip-pinctrl.dtsi
new file mode 100644
index 00000000000..3aae585eb44
--- /dev/null
+++ b/boards/riscv/qemu_riscv32/qemu_riscv32_xip-pinctrl.dtsi
@@ -0,0 +1,17 @@
+/*
+ * Copyright (c) 2022 Antmicro <www.antmicro.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <dt-bindings/pinctrl/sifive-pinctrl.h>
+
+&pinctrl {
+	/* UART0 */
+	uart0_rx_default: uart0_rx_default {
+		pinmux = <16 SIFIVE_PINMUX_IOF0>;
+	};
+	uart0_tx_default: uart0_tx_default {
+		pinmux = <17 SIFIVE_PINMUX_IOF0>;
+	};
+};