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dts: arm: ambiq: Add I2C instances to SoC 

This commit instantiates the I2C peripherals.

Signed-off-by: Mateusz Sierszulski <msierszulski@antmicro.com>
This commit is contained in:
Mateusz Sierszulski 2023-06-29 14:28:58 +02:00 committed by Carles Cufí
parent 47d0e79444
commit a72d8dbcb4
2 changed files with 153 additions and 0 deletions
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64
boards/arm/apollo4p_evb/apollo4p_evb-pinctrl.dtsi
View File

@ -16,4 +16,68 @@
input-enable;
};
};
i2c0_default: i2c0_default {
group1 {
pinmux = <M0SCL_P5>, <M0SDAWIR3_P6>;
drive-open-drain;
drive-strength = "0.5";
bias-pull-up;
};
};
i2c1_default: i2c1_default {
group1 {
pinmux = <M1SCL_P8>, <M1SDAWIR3_P9>;
drive-open-drain;
drive-strength = "0.5";
bias-pull-up;
};
};
i2c2_default: i2c2_default {
group1 {
pinmux = <M2SCL_P25>, <M2SDAWIR3_P26>;
drive-open-drain;
drive-strength = "0.5";
bias-pull-up;
};
};
i2c3_default: i2c3_default {
group1 {
pinmux = <M3SCL_P31>, <M3SDAWIR3_P32>;
drive-open-drain;
drive-strength = "0.5";
bias-pull-up;
};
};
i2c4_default: i2c4_default {
group1 {
pinmux = <M4SCL_P34>, <M4SDAWIR3_P35>;
drive-open-drain;
drive-strength = "0.5";
bias-pull-up;
};
};
i2c5_default: i2c5_default {
group1 {
pinmux = <M5SCL_P47>, <M5SDAWIR3_P48>;
drive-open-drain;
drive-strength = "0.5";
bias-pull-up;
};
};
i2c6_default: i2c6_default {
group1 {
pinmux = <M6SCL_P61>, <M6SDAWIR3_P62>;
drive-open-drain;
drive-strength = "0.5";
bias-pull-up;
};
};
i2c7_default: i2c7_default {
group1 {
pinmux = <M7SCL_P22>, <M7SDAWIR3_P23>;
drive-open-drain;
drive-strength = "0.5";
bias-pull-up;
};
};
};

89
dts/arm/ambiq/ambiq_apollo4p.dtsi
View File

@ -2,6 +2,7 @@
#include <arm/armv7-m.dtsi>
#include <mem.h>
#include <zephyr/dt-bindings/i2c/i2c.h>
/ {
clocks {
@ -101,6 +102,94 @@
ambiq,pwrcfg = <&pwrcfg 0x4 0x1000>;
};
i2c0: i2c@40050000 {
compatible = "ambiq,i2c";
reg = <0x40050000 0x1000>;
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <6 0>;
status = "disabled";
ambiq,pwrcfg = <&pwrcfg 0x4 0x2>;
};
i2c1: i2c@40051000 {
compatible = "ambiq,i2c";
reg = <0x40051000 0x1000>;
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <7 0>;
status = "disabled";
ambiq,pwrcfg = <&pwrcfg 0x4 0x4>;
};
i2c2: i2c@40052000 {
compatible = "ambiq,i2c";
reg = <0x40052000 0x1000>;
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <8 0>;
status = "disabled";
ambiq,pwrcfg = <&pwrcfg 0x4 0x8>;
};
i2c3: i2c@40053000 {
compatible = "ambiq,i2c";
reg = <0x40053000 0x1000>;
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <9 0>;
status = "disabled";
ambiq,pwrcfg = <&pwrcfg 0x4 0x10>;
};
i2c4: i2c@40054000 {
compatible = "ambiq,i2c";
reg = <0x40054000 0x1000>;
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <10 0>;
status = "disabled";
ambiq,pwrcfg = <&pwrcfg 0x4 0x20>;
};
i2c5: i2c@40055000 {
compatible = "ambiq,i2c";
reg = <0x40055000 0x1000>;
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <11 0>;
status = "disabled";
ambiq,pwrcfg = <&pwrcfg 0x4 0x40>;
};
i2c6: i2c@40056000 {
compatible = "ambiq,i2c";
reg = <0x40056000 0x1000>;
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <12 0>;
status = "disabled";
ambiq,pwrcfg = <&pwrcfg 0x4 0x80>;
};
i2c7: i2c@40057000 {
compatible = "ambiq,i2c";
reg = <0x40057000 0x1000>;
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <13 0>;
status = "disabled";
ambiq,pwrcfg = <&pwrcfg 0x4 0x100>;
};
pinctrl: pin-controller@40010000 {
compatible = "ambiq,apollo4-pinctrl";
reg = <0x40010000 0x800>;