From a6ffdd3e47f32de063368ceb85d1a5bb3d674060 Mon Sep 17 00:00:00 2001 From: Mathieu Choplain Date: Tue, 15 Oct 2024 11:40:53 +0200 Subject: [PATCH] dts: arm: st: wb0: add I2C and SPI nodes Add I2C and SPI Device Tree nodes in SoC DTSI files to allow usage of these peripherals. Note that the SPI driver requires no modification to be functional on WB0. Signed-off-by: Mathieu Choplain --- dts/arm/st/wb0/stm32wb0.dtsi | 22 ++++++++++++++++++++++ dts/arm/st/wb0/stm32wb07.dtsi | 32 ++++++++++++++++++++++++++++++++ 2 files changed, 54 insertions(+) diff --git a/dts/arm/st/wb0/stm32wb0.dtsi b/dts/arm/st/wb0/stm32wb0.dtsi index 7a8454fa011..157438a2e85 100644 --- a/dts/arm/st/wb0/stm32wb0.dtsi +++ b/dts/arm/st/wb0/stm32wb0.dtsi @@ -195,6 +195,28 @@ interrupts = <9 0>; status = "disabled"; }; + + i2c1: i2c@41000000 { + compatible = "st,stm32-i2c-v2"; + clock-frequency = ; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x41000000 DT_SIZE_K(1)>; + clocks = <&rcc STM32_CLOCK_BUS_APB1 (1 << 21)>; + interrupts = <3 0>; + interrupt-names = "combined"; + status = "disabled"; + }; + + spi3: spi@41007000 { + compatible = "st,stm32-spi-fifo", "st,stm32-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x41007000 DT_SIZE_K(1)>; + clocks = <&rcc STM32_CLOCK_BUS_APB1 (1 << 14)>; + interrupts = <7 0>; + status = "disabled"; + }; }; }; diff --git a/dts/arm/st/wb0/stm32wb07.dtsi b/dts/arm/st/wb0/stm32wb07.dtsi index b69008ed2d8..d6fbf5acc93 100644 --- a/dts/arm/st/wb0/stm32wb07.dtsi +++ b/dts/arm/st/wb0/stm32wb07.dtsi @@ -15,5 +15,37 @@ reg = <0x10040000 DT_SIZE_K(256)>; }; }; + + i2c2: i2c@41001000 { + compatible = "st,stm32-i2c-v2"; + clock-frequency = ; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x41001000 DT_SIZE_K(1)>; + clocks = <&rcc STM32_CLOCK_BUS_APB1 (1 << 23)>; + interrupts = <4 0>; + interrupt-names = "combined"; + status = "disabled"; + }; + + spi1: spi@41002000 { + compatible = "st,stm32-spi-fifo", "st,stm32-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x41002000 DT_SIZE_K(1)>; + clocks = <&rcc STM32_CLOCK_BUS_APB1 (1 << 0)>; + interrupts = <5 0>; + status = "disabled"; + }; + + spi2: spi@41003000 { + compatible = "st,stm32-spi-fifo", "st,stm32-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x41003000 DT_SIZE_K(1)>; + clocks = <&rcc STM32_CLOCK_BUS_APB1 (1 << 12)>; + interrupts = <6 0>; + status = "disabled"; + }; }; };