soc: arm: ambiq: apollo3: Add support for Apollo3 Blue Plus SoC

Add all required parts (new SoC family/series, device tree) for
the Ambiq Apollo3 Blue Plus SoC.

Signed-off-by: Hao Luo <hluo@ambiq.com>

MAINTAINERS.yml

@@ -244,6 +244,7 @@ Ambiq Platforms:
   status: odd fixes
   collaborators:
     - aaronyegx
+    - HaoLuo
     - RichardSWheatley
   files:
     - soc/ambiq/

dts/arm/ambiq/ambiq_apollo3p_blue.dtsi

@@ -0,0 +1,186 @@
+/* SPDX-License-Identifier: Apache-2.0 */
+
+#include <arm/armv7-m.dtsi>
+#include <mem.h>
+#include <freq.h>
+#include <zephyr/dt-bindings/i2c/i2c.h>
+#include <zephyr/dt-bindings/gpio/gpio.h>
+
+/ {
+	clocks {
+		uartclk: apb-pclk {
+			compatible = "fixed-clock";
+			clock-frequency = <DT_FREQ_M(24)>;
+			#clock-cells = <0>;
+		};
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			compatible = "arm,cortex-m4f";
+			reg = <0>;
+		};
+	};
+
+	/* Flash region */
+	flash0: flash@C000 {
+		compatible = "soc-nv-flash";
+		reg = <0x0000C000 0x1F4000>;
+	};
+
+	/* TCM */
+	tcm: tcm@10000000 {
+		compatible = "zephyr,memory-region";
+		reg = <0x10000000 0x10000>;
+		zephyr,memory-region = "ITCM";
+	};
+
+	/* SRAM */
+	sram0: memory@10010000 {
+		compatible = "mmio-sram";
+		reg = <0x10010000 0xB0000>;
+	};
+
+	soc {
+		compatible = "ambiq,apollo3p-blue", "ambiq,apollo3x", "simple-bus";
+
+		pwrcfg: pwrcfg@40021000 {
+			compatible = "ambiq,pwrctrl";
+			reg = <0x40021000 0x400>;
+			#pwrcfg-cells = <2>;
+		};
+
+		stimer0: stimer@40008140 {
+			compatible = "ambiq,stimer";
+			reg = <0x40008140 0x80>;
+			interrupts = <23 0>;
+			status = "okay";
+		};
+
+		counter0: counter@40008000 {
+			compatible = "ambiq,counter";
+			reg = <0x40008000 0x80>;
+			interrupts = <14 0>;
+			status = "disabled";
+		};
+
+		uart0: uart@4001c000 {
+			compatible = "ambiq,uart", "arm,pl011";
+			reg = <0x4001c000 0x1000>;
+			interrupts = <15 0>;
+			interrupt-names = "UART0";
+			status = "disabled";
+			clocks = <&uartclk>;
+			ambiq,pwrcfg = <&pwrcfg 0x8 0x80>;
+		};
+
+		uart1: uart@4001d000 {
+			compatible = "ambiq,uart", "arm,pl011";
+			reg = <0x4001d000 0x1000>;
+			interrupts = <16 0>;
+			interrupt-names = "UART1";
+			status = "disabled";
+			clocks = <&uartclk>;
+			ambiq,pwrcfg = <&pwrcfg 0x8 0x100>;
+		};
+
+		iom0: iom@50004000 {
+			reg = <0x50004000 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <6 0>;
+			status = "disabled";
+			ambiq,pwrcfg = <&pwrcfg 0x8 0x2>;
+		};
+
+		iom1: iom@50005000 {
+			reg = <0x50005000 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <7 0>;
+			status = "disabled";
+			ambiq,pwrcfg = <&pwrcfg 0x8 0x4>;
+		};
+
+		iom2: iom@50006000 {
+			reg = <0x50006000 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <8 0>;
+			status = "disabled";
+			ambiq,pwrcfg = <&pwrcfg 0x8 0x8>;
+		};
+
+		iom3: iom@50007000 {
+			reg = <0x50007000 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <9 0>;
+			status = "disabled";
+			ambiq,pwrcfg = <&pwrcfg 0x8 0x10>;
+		};
+
+		iom4: iom@50008000 {
+			reg = <0x50008000 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <10 0>;
+			status = "disabled";
+			ambiq,pwrcfg = <&pwrcfg 0x8 0x20>;
+		};
+
+		iom5: iom@50009000 {
+			reg = <0x50009000 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <11 0>;
+			status = "disabled";
+			ambiq,pwrcfg = <&pwrcfg 0x8 0x40>;
+		};
+
+		mspi0: spi@50014000 {
+			compatible = "ambiq,mspi";
+			reg = <0x50014000 0x400>;
+			interrupts = <20 0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+			ambiq,pwrcfg = <&pwrcfg 0x8 0x800>;
+		};
+
+		mspi1: spi@50015000 {
+			compatible = "ambiq,mspi";
+			reg = <0x50015000 0x400>;
+			interrupts = <32 0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+			ambiq,pwrcfg = <&pwrcfg 0x8 0x1000>;
+		};
+
+		mspi2: spi@50016000 {
+			compatible = "ambiq,mspi";
+			reg = <0x50016000 0x400>;
+			interrupts = <33 0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+			ambiq,pwrcfg = <&pwrcfg 0x8 0x2000>;
+		};
+
+		wdt0: watchdog@40024000 {
+			compatible = "ambiq,watchdog";
+			reg = <0x40024000 0x400>;
+			interrupts = <1 0>;
+			clock-frequency = <16>;
+			status = "disabled";
+		};
+	};
+};
+
+&nvic {
+	arm,num-irq-priority-bits = <3>;
+};

modules/hal_ambiq/Kconfig

@@ -4,7 +4,7 @@
 
 config AMBIQ_HAL
 	bool "Ambiq HAL drivers support"
-	depends on SOC_SERIES_APOLLO4X
+	depends on SOC_SERIES_APOLLO4X || SOC_SERIES_APOLLO3X
 	help
 	  Use the Ambiq HAL
 

soc/ambiq/apollo3x/CMakeLists.txt

@@ -0,0 +1,9 @@
+# Copyright (c) 2023 Ambiq Micro Inc. <www.ambiq.com>
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+zephyr_sources(soc.c)
+zephyr_include_directories(.)
+
+set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")

soc/ambiq/apollo3x/Kconfig

@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: Apache-2.0
+#
+# Copyright (c) 2023 Ambiq Micro Inc. <www.ambiq.com>
+
+config SOC_SERIES_APOLLO3X
+	select ARM
+	select CPU_CORTEX_M4
+	select CPU_CORTEX_M_HAS_DWT
+	select CPU_HAS_FPU
+	select CPU_HAS_ARM_MPU
+	select HAS_SWO
+	select AMBIQ_HAL

soc/ambiq/apollo3x/Kconfig.defconfig

@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: Apache-2.0
+#
+# Copyright (c) 2023 Ambiq Micro Inc. <www.ambiq.com>
+
+if SOC_SERIES_APOLLO3X
+
+rsource "Kconfig.defconfig.apollo3*"
+
+endif # SOC_SERIES_APOLLO3X

soc/ambiq/apollo3x/Kconfig.defconfig.apollo3p_blue

@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: Apache-2.0
+#
+# Copyright (c) 2023 Ambiq Micro Inc. <www.ambiq.com>
+
+if SOC_APOLLO3P_BLUE
+
+config NUM_IRQS
+	default 33
+
+endif # SOC_APOLLO3P_BLUE

soc/ambiq/apollo3x/Kconfig.soc

@@ -0,0 +1,28 @@
+# SPDX-License-Identifier: Apache-2.0
+#
+# Copyright (c) 2023 Ambiq Micro Inc. <www.ambiq.com>
+
+config SOC_SERIES_APOLLO3X
+	bool
+	select SOC_FAMILY_AMBIQ
+	help
+	  Apollo3 Series MCU
+
+config SOC_APOLLO3P_BLUE
+	bool
+	select SOC_SERIES_APOLLO3X
+	help
+	  Apollo3P Blue
+
+config SOC_APOLLO3_BLUE
+	bool
+	select SOC_SERIES_APOLLO3X
+	help
+	  Apollo3 Blue
+
+config SOC_SERIES
+	default "apollo3x" if SOC_SERIES_APOLLO3X
+
+config SOC
+	default "apollo3_blue" if SOC_APOLLO3_BLUE
+	default "apollo3p_blue" if SOC_APOLLO3P_BLUE

soc/ambiq/apollo3x/soc.c

@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2023 Ambiq Micro Inc. <www.ambiq.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/init.h>
+
+#include <am_mcu_apollo.h>
+
+static int arm_apollo3_init(void)
+{
+
+	/* Initialize for low power in the power control block */
+	am_hal_pwrctrl_low_power_init();
+
+	/* Disable the RTC. */
+	am_hal_rtc_osc_disable();
+
+	return 0;
+}
+
+SYS_INIT(arm_apollo3_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);

soc/ambiq/apollo3x/soc.h

@@ -0,0 +1,16 @@
+/*
+ * Copyright (c) 2023 Ambiq Micro Inc. <www.ambiq.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef __SOC_H__
+#define __SOC_H__
+
+#if defined(CONFIG_SOC_APOLLO3P_BLUE)
+#include <apollo3p.h>
+#elif defined(CONFIG_SOC_APOLLO3_BLUE)
+#include <apollo3.h>
+#endif
+
+#endif /* __SOC_H__ */

soc/ambiq/soc.yml

@@ -5,3 +5,7 @@ family:
     socs:
     - name: apollo4p
     - name: apollo4p_blue
+  - name: apollo3x
+    socs:
+    - name: apollo3_blue
+    - name: apollo3p_blue

west.yml

@@ -142,7 +142,7 @@ manifest:
       groups:
         - hal
     - name: hal_ambiq
-      revision: ff4ca358d730536addf336c40c3faa4ebf1df00a
+      revision: 326d061d85c4384ff7811ab04f3ed3c66d436fb1
       path: modules/hal/ambiq
       groups:
         - hal