From 92eadf06b8dd03b75e9546e023a17708748bc71f Mon Sep 17 00:00:00 2001
From: Jamie McCrae <jamie.mccrae@nordicsemi.no>
Date: Wed, 14 Feb 2024 08:25:39 +0000
Subject: [PATCH] soc: opentitan: Port to HWMv2

Ports the SoC configuration to hardware model version 2

Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
---
 .../riscv => lowrisc}/opentitan/CMakeLists.txt            | 0
 .../opentitan/Kconfig.soc => lowrisc/opentitan/Kconfig}   | 1 -
 .../riscv => lowrisc}/opentitan/Kconfig.defconfig         | 3 ---
 soc/lowrisc/opentitan/Kconfig.soc                         | 8 ++++++++
 soc/{soc_legacy/riscv => lowrisc}/opentitan/rom_header.S  | 0
 soc/{soc_legacy/riscv => lowrisc}/opentitan/rom_header.ld | 0
 soc/{soc_legacy/riscv => lowrisc}/opentitan/soc.c         | 0
 soc/lowrisc/opentitan/soc.yml                             | 2 ++
 8 files changed, 10 insertions(+), 4 deletions(-)
 rename soc/{soc_legacy/riscv => lowrisc}/opentitan/CMakeLists.txt (100%)
 rename soc/{soc_legacy/riscv/opentitan/Kconfig.soc => lowrisc/opentitan/Kconfig} (94%)
 rename soc/{soc_legacy/riscv => lowrisc}/opentitan/Kconfig.defconfig (91%)
 create mode 100644 soc/lowrisc/opentitan/Kconfig.soc
 rename soc/{soc_legacy/riscv => lowrisc}/opentitan/rom_header.S (100%)
 rename soc/{soc_legacy/riscv => lowrisc}/opentitan/rom_header.ld (100%)
 rename soc/{soc_legacy/riscv => lowrisc}/opentitan/soc.c (100%)
 create mode 100644 soc/lowrisc/opentitan/soc.yml

diff --git a/soc/soc_legacy/riscv/opentitan/CMakeLists.txt b/soc/lowrisc/opentitan/CMakeLists.txt
similarity index 100%
rename from soc/soc_legacy/riscv/opentitan/CMakeLists.txt
rename to soc/lowrisc/opentitan/CMakeLists.txt
diff --git a/soc/soc_legacy/riscv/opentitan/Kconfig.soc b/soc/lowrisc/opentitan/Kconfig
similarity index 94%
rename from soc/soc_legacy/riscv/opentitan/Kconfig.soc
rename to soc/lowrisc/opentitan/Kconfig
index c76cfe013b1..25670a967c6 100644
--- a/soc/soc_legacy/riscv/opentitan/Kconfig.soc
+++ b/soc/lowrisc/opentitan/Kconfig
@@ -2,7 +2,6 @@
 # SPDX-License-Identifier: Apache-2.0
 
 config SOC_OPENTITAN
-	bool "OpenTitan implementation"
 	select ATOMIC_OPERATIONS_C
 	select INCLUDE_RESET_VECTOR
 	select RISCV_ISA_RV32I
diff --git a/soc/soc_legacy/riscv/opentitan/Kconfig.defconfig b/soc/lowrisc/opentitan/Kconfig.defconfig
similarity index 91%
rename from soc/soc_legacy/riscv/opentitan/Kconfig.defconfig
rename to soc/lowrisc/opentitan/Kconfig.defconfig
index 4b067ef76af..b77a9405fbe 100644
--- a/soc/soc_legacy/riscv/opentitan/Kconfig.defconfig
+++ b/soc/lowrisc/opentitan/Kconfig.defconfig
@@ -3,9 +3,6 @@
 
 if SOC_OPENTITAN
 
-config SOC
-	default "opentitan"
-
 config SYS_CLOCK_HW_CYCLES_PER_SEC
 	default 1000000
 
diff --git a/soc/lowrisc/opentitan/Kconfig.soc b/soc/lowrisc/opentitan/Kconfig.soc
new file mode 100644
index 00000000000..bf5ff0780e9
--- /dev/null
+++ b/soc/lowrisc/opentitan/Kconfig.soc
@@ -0,0 +1,8 @@
+# Copyright (c) 2023 Rivos Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_OPENTITAN
+	bool
+
+config SOC
+	default "opentitan" if SOC_OPENTITAN
diff --git a/soc/soc_legacy/riscv/opentitan/rom_header.S b/soc/lowrisc/opentitan/rom_header.S
similarity index 100%
rename from soc/soc_legacy/riscv/opentitan/rom_header.S
rename to soc/lowrisc/opentitan/rom_header.S
diff --git a/soc/soc_legacy/riscv/opentitan/rom_header.ld b/soc/lowrisc/opentitan/rom_header.ld
similarity index 100%
rename from soc/soc_legacy/riscv/opentitan/rom_header.ld
rename to soc/lowrisc/opentitan/rom_header.ld
diff --git a/soc/soc_legacy/riscv/opentitan/soc.c b/soc/lowrisc/opentitan/soc.c
similarity index 100%
rename from soc/soc_legacy/riscv/opentitan/soc.c
rename to soc/lowrisc/opentitan/soc.c
diff --git a/soc/lowrisc/opentitan/soc.yml b/soc/lowrisc/opentitan/soc.yml
new file mode 100644
index 00000000000..51ebb26a55c
--- /dev/null
+++ b/soc/lowrisc/opentitan/soc.yml
@@ -0,0 +1,2 @@
+socs:
+- name: opentitan