drivers: spi: Add Ambiq MSPI driver
This commit adds MSPI driver for Apollo4 SoCs. Signed-off-by: Mateusz Sierszulski <msierszulski@antmicro.com>
This commit is contained in:
Mateusz Sierszulski
Carles Cufí
parent
3d713a42e8
commit
8db11e6a0a
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@ -43,6 +43,7 @@ zephyr_library_sources_ifdef(CONFIG_SPI_OPENTITAN spi_opentitan.c)
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zephyr_library_sources_ifdef(CONFIG_SPI_NUMAKER spi_numaker.c)
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zephyr_library_sources_ifdef(CONFIG_SPI_AMBIQ spi_ambiq.c)
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zephyr_library_sources_ifdef(CONFIG_SPI_RPI_PICO_PIO spi_rpi_pico_pio.c)
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zephyr_library_sources_ifdef(CONFIG_MSPI_AMBIQ mspi_ambiq.c)
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zephyr_library_sources_ifdef(CONFIG_SPI_RTIO spi_rtio.c)
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zephyr_library_sources_ifdef(CONFIG_SPI_ASYNC spi_signal.c)
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@ -13,3 +13,12 @@ config SPI_AMBIQ
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select AMBIQ_HAL_USE_SPI
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help
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Enable driver for Ambiq SPI.
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config MSPI_AMBIQ
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bool "AMBIQ MSPI driver"
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default y
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depends on DT_HAS_AMBIQ_MSPI_ENABLED
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select AMBIQ_HAL
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select AMBIQ_HAL_USE_MSPI
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help
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Enable driver for Ambiq MSPI.
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@ -0,0 +1,253 @@
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/*
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* Copyright (c) 2023 Antmicro <www.antmicro.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT ambiq_mspi
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#include <zephyr/logging/log.h>
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LOG_MODULE_REGISTER(mspi_ambiq);
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#include <zephyr/drivers/spi.h>
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#include <zephyr/drivers/pinctrl.h>
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#include <zephyr/kernel.h>
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#include "spi_context.h"
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#include <am_mcu_apollo.h>
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#define SPI_WORD_SIZE 8
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#define MSPI_MAX_FREQ 96000000
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#define MSPI_TIMEOUT_US 1000000
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#define PWRCTRL_MAX_WAIT_US 5
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#define MSPI_BUSY BIT(2)
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typedef int (*ambiq_mspi_pwr_func_t)(void);
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struct mspi_ambiq_config {
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uint32_t base;
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int size;
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uint32_t clock_freq;
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const struct pinctrl_dev_config *pcfg;
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ambiq_mspi_pwr_func_t pwr_func;
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};
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struct mspi_ambiq_data {
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struct spi_context ctx;
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void *mspiHandle;
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am_hal_mspi_dev_config_t mspicfg;
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};
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static int mspi_set_freq(uint32_t freq)
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{
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uint32_t d = MSPI_MAX_FREQ / freq;
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switch (d) {
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case AM_HAL_MSPI_CLK_96MHZ:
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case AM_HAL_MSPI_CLK_48MHZ:
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case AM_HAL_MSPI_CLK_32MHZ:
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case AM_HAL_MSPI_CLK_24MHZ:
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case AM_HAL_MSPI_CLK_16MHZ:
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case AM_HAL_MSPI_CLK_12MHZ:
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case AM_HAL_MSPI_CLK_8MHZ:
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case AM_HAL_MSPI_CLK_6MHZ:
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case AM_HAL_MSPI_CLK_4MHZ:
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case AM_HAL_MSPI_CLK_3MHZ:
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break;
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default:
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LOG_ERR("Frequency not supported!");
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d = AM_HAL_MSPI_CLK_INVALID;
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break;
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}
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return d;
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}
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static int mspi_config(const struct device *dev, const struct spi_config *config)
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{
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struct mspi_ambiq_data *data = dev->data;
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int ret;
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am_hal_mspi_dev_config_t mspicfg = {0};
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if (config->operation & SPI_HALF_DUPLEX) {
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LOG_ERR("Half-duplex not supported");
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return -ENOTSUP;
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}
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if (SPI_WORD_SIZE_GET(config->operation) != 8) {
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LOG_ERR("Word size must be %d", SPI_WORD_SIZE);
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return -ENOTSUP;
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}
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if ((config->operation & SPI_LINES_MASK) != SPI_LINES_SINGLE) {
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LOG_ERR("Only single mode is currently supported");
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return -ENOTSUP;
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}
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if (config->operation & SPI_LOCK_ON) {
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LOG_ERR("Lock On not supported");
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return -ENOTSUP;
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}
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if (config->operation & SPI_TRANSFER_LSB) {
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LOG_ERR("LSB first not supported");
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return -ENOTSUP;
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}
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if (config->operation & (SPI_MODE_CPOL | SPI_MODE_CPHA)) {
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if (config->operation & (SPI_MODE_CPOL && SPI_MODE_CPHA)) {
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mspicfg.eSpiMode = AM_HAL_MSPI_SPI_MODE_3;
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} else if (config->operation & SPI_MODE_CPOL) {
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mspicfg.eSpiMode = AM_HAL_MSPI_SPI_MODE_2;
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} else if (config->operation & SPI_MODE_CPHA) {
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mspicfg.eSpiMode = AM_HAL_MSPI_SPI_MODE_1;
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} else {
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mspicfg.eSpiMode = AM_HAL_MSPI_SPI_MODE_0;
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}
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}
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mspicfg.eClockFreq = mspi_set_freq(config->frequency);
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if (mspicfg.eClockFreq == AM_HAL_MSPI_CLK_INVALID) {
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return -ENOTSUP;
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}
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mspicfg.eDeviceConfig = AM_HAL_MSPI_FLASH_SERIAL_CE0;
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ret = am_hal_mspi_disable(data->mspiHandle);
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if (ret) {
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return ret;
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}
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ret = am_hal_mspi_device_configure(data->mspiHandle, &mspicfg);
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if (ret) {
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return ret;
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}
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ret = am_hal_mspi_enable(data->mspiHandle);
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return ret;
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}
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static int mspi_ambiq_xfer(const struct device *dev, const struct spi_config *config)
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{
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struct mspi_ambiq_data *data = dev->data;
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struct spi_context *ctx = &data->ctx;
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int ret;
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am_hal_mspi_pio_transfer_t trans = {0};
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trans.bSendAddr = true;
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trans.bSendInstr = true;
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trans.ui16DeviceInstr = *ctx->tx_buf;
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spi_context_update_tx(ctx, 1, 1);
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trans.ui32DeviceAddr = *ctx->tx_buf;
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if (ctx->rx_buf != NULL) {
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spi_context_update_rx(ctx, 1, ctx->rx_len);
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trans.eDirection = AM_HAL_MSPI_RX;
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trans.pui32Buffer = (uint32_t *)ctx->rx_buf;
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trans.ui32NumBytes = ctx->rx_len;
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} else if (ctx->tx_buf != NULL) {
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spi_context_update_tx(ctx, 1, 1);
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trans.eDirection = AM_HAL_MSPI_TX;
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trans.pui32Buffer = (uint32_t *)ctx->tx_buf;
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trans.ui32NumBytes = ctx->tx_len;
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}
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ret = am_hal_mspi_blocking_transfer(data->mspiHandle, &trans, MSPI_TIMEOUT_US);
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spi_context_complete(ctx, dev, 0);
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return ret;
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}
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static int mspi_ambiq_transceive(const struct device *dev, const struct spi_config *config,
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const struct spi_buf_set *tx_bufs,
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const struct spi_buf_set *rx_bufs)
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{
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struct mspi_ambiq_data *data = dev->data;
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int ret = mspi_config(dev, config);
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if (ret) {
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return ret;
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}
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if (!tx_bufs && !rx_bufs) {
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return 0;
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}
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spi_context_buffers_setup(&data->ctx, tx_bufs, rx_bufs, 1);
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ret = mspi_ambiq_xfer(dev, config);
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return ret;
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}
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static int mspi_ambiq_release(const struct device *dev, const struct spi_config *config)
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{
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const struct mspi_ambiq_config *cfg = dev->config;
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if (sys_read32(cfg->base) & MSPI_BUSY) {
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return -EBUSY;
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}
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return 0;
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}
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static struct spi_driver_api mspi_ambiq_driver_api = {
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.transceive = mspi_ambiq_transceive,
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.release = mspi_ambiq_release,
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};
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static int mspi_ambiq_init(const struct device *dev)
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{
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struct mspi_ambiq_data *data = dev->data;
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const struct mspi_ambiq_config *cfg = dev->config;
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am_hal_mspi_config_t mspiCfg = {0};
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mspiCfg.pTCB = NULL;
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int ret = am_hal_mspi_initialize((cfg->base - REG_MSPI_BASEADDR) / (cfg->size * 4),
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&data->mspiHandle);
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if (ret) {
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return ret;
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}
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ret = cfg->pwr_func();
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ret = am_hal_mspi_configure(data->mspiHandle, &mspiCfg);
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if (ret) {
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return ret;
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}
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ret = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT);
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return ret;
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}
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#define AMBIQ_MSPI_DEFINE(n) \
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PINCTRL_DT_INST_DEFINE(n); \
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static int pwr_on_ambiq_mspi_##n(void) \
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{ \
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uint32_t addr = DT_REG_ADDR(DT_INST_PHANDLE(n, ambiq_pwrcfg)) + \
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DT_INST_PHA(n, ambiq_pwrcfg, offset); \
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sys_write32((sys_read32(addr) | DT_INST_PHA(n, ambiq_pwrcfg, mask)), addr); \
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k_busy_wait(PWRCTRL_MAX_WAIT_US); \
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return 0; \
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} \
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static struct mspi_ambiq_data mspi_ambiq_data##n = { \
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SPI_CONTEXT_INIT_SYNC(mspi_ambiq_data##n, ctx)}; \
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static const struct mspi_ambiq_config mspi_ambiq_config##n = { \
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.base = DT_INST_REG_ADDR(n), \
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.size = DT_INST_REG_SIZE(n), \
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.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \
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.pwr_func = pwr_on_ambiq_mspi_##n, \
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}; \
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DEVICE_DT_INST_DEFINE(n, mspi_ambiq_init, NULL, &mspi_ambiq_data##n, \
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&mspi_ambiq_config##n, POST_KERNEL, CONFIG_SPI_INIT_PRIORITY, \
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&mspi_ambiq_driver_api);
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DT_INST_FOREACH_STATUS_OKAY(AMBIQ_MSPI_DEFINE)
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@ -0,0 +1,18 @@
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# Copyright (c) 2023 Antmicro <www.antmicro.com>
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# SPDX-License-Identifier: Apache-2.0
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description: Ambiq MSPI
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compatible: "ambiq,mspi"
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include: [spi-controller.yaml, pinctrl-device.yaml, ambiq-pwrcfg.yaml]
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properties:
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reg:
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required: true
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interrupts:
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required: true
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ambiq,pwrcfg:
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required: true
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@ -40,4 +40,9 @@ config AMBIQ_HAL_USE_SPI
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help
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Use the SPI driver from Ambiq HAL
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config AMBIQ_HAL_USE_MSPI
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bool
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help
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Use the MSPI driver from Ambiq HAL
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endif # AMBIQ_HAL
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