diff --git a/drivers/dac/dac_gd32.c b/drivers/dac/dac_gd32.c
index a7d9b3a9ab7..fe38c006a44 100644
--- a/drivers/dac/dac_gd32.c
+++ b/drivers/dac/dac_gd32.c
@@ -7,12 +7,14 @@
 #define DT_DRV_COMPAT gd_gd32_dac
 
 #include <errno.h>
+
+#include <zephyr/drivers/clock_control.h>
+#include <zephyr/drivers/clock_control/gd32.h>
 #include <zephyr/drivers/pinctrl.h>
 #include <zephyr/drivers/reset.h>
 #include <zephyr/drivers/dac.h>
 
 #include <gd32_dac.h>
-#include <gd32_rcu.h>
 
 #include <zephyr/logging/log.h>
 LOG_MODULE_REGISTER(dac_gd32, CONFIG_DAC_LOG_LEVEL);
@@ -29,7 +31,7 @@ LOG_MODULE_REGISTER(dac_gd32, CONFIG_DAC_LOG_LEVEL);
 
 struct dac_gd32_config {
 	uint32_t reg;
-	uint32_t rcu_periph_clock;
+	uint16_t clkid;
 	struct reset_dt_spec reset;
 	const struct pinctrl_dev_config *pcfg;
 	uint32_t num_channels;
@@ -149,7 +151,8 @@ static int dac_gd32_init(const struct device *dev)
 		return ret;
 	}
 
-	rcu_periph_clock_enable(cfg->rcu_periph_clock);
+	(void)clock_control_on(GD32_CLOCK_CONTROLLER,
+			       (clock_control_subsys_t *)&cfg->clkid);
 
 	(void)reset_line_toggle_dt(&cfg->reset);
 
@@ -162,7 +165,7 @@ static struct dac_gd32_data dac_gd32_data_0;
 
 static const struct dac_gd32_config dac_gd32_cfg_0 = {
 	.reg = DT_INST_REG_ADDR(0),
-	.rcu_periph_clock = DT_INST_PROP(0, rcu_periph_clock),
+	.clkid = DT_INST_CLOCKS_CELL(0, id),
 	.reset = RESET_DT_SPEC_INST_GET(0),
 	.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(0),
 	.num_channels = DT_INST_PROP(0, num_channels),
diff --git a/dts/arm/gigadevice/gd32e10x/gd32e10x.dtsi b/dts/arm/gigadevice/gd32e10x/gd32e10x.dtsi
index f84024d09f9..08bf4c63dda 100644
--- a/dts/arm/gigadevice/gd32e10x/gd32e10x.dtsi
+++ b/dts/arm/gigadevice/gd32e10x/gd32e10x.dtsi
@@ -108,7 +108,7 @@
 		dac: dac@40007400 {
 			compatible = "gd,gd32-dac";
 			reg = <0x40007400 0x400>;
-			rcu-periph-clock = <0x71d>;
+			clocks = <&cctl GD32_CLOCK_DAC>;
 			resets = <&rctl GD32_RESET_DAC>;
 			num-channels = <2>;
 			status = "disabled";
diff --git a/dts/arm/gigadevice/gd32e50x/gd32e50x.dtsi b/dts/arm/gigadevice/gd32e50x/gd32e50x.dtsi
index 040e3736e2e..159a86ee5d8 100644
--- a/dts/arm/gigadevice/gd32e50x/gd32e50x.dtsi
+++ b/dts/arm/gigadevice/gd32e50x/gd32e50x.dtsi
@@ -125,7 +125,7 @@
 		dac: dac@40007400 {
 			compatible = "gd,gd32-dac";
 			reg = <0x40007400 0x400>;
-			rcu-periph-clock = <0x71d>;
+			clocks = <&cctl GD32_CLOCK_DAC>;
 			resets = <&rctl GD32_RESET_DAC>;
 			num-channels = <2>;
 			status = "disabled";
diff --git a/dts/arm/gigadevice/gd32f3x0/gd32f350.dtsi b/dts/arm/gigadevice/gd32f3x0/gd32f350.dtsi
index ff90a79f8b1..43dbe4b3a5d 100644
--- a/dts/arm/gigadevice/gd32f3x0/gd32f350.dtsi
+++ b/dts/arm/gigadevice/gd32f3x0/gd32f350.dtsi
@@ -12,7 +12,7 @@
 		dac: dac@40007400 {
 			compatible = "gd,gd32-dac";
 			reg = <0x40007400 0x400>;
-			rcu-periph-clock = <0x71d>;
+			clocks = <&cctl GD32_CLOCK_DAC>;
 			resets = <&rctl GD32_RESET_DAC>;
 			num-channels = <1>;
 			status = "disabled";
diff --git a/dts/arm/gigadevice/gd32f4xx/gd32f4xx.dtsi b/dts/arm/gigadevice/gd32f4xx/gd32f4xx.dtsi
index caaa9dd6c47..df152d39f55 100644
--- a/dts/arm/gigadevice/gd32f4xx/gd32f4xx.dtsi
+++ b/dts/arm/gigadevice/gd32f4xx/gd32f4xx.dtsi
@@ -141,7 +141,7 @@
 		dac: dac@40007400 {
 			compatible = "gd,gd32-dac";
 			reg = <0x40007400 0x400>;
-			rcu-periph-clock = <0x101d>;
+			clocks = <&cctl GD32_CLOCK_DAC>;
 			resets = <&rctl GD32_RESET_DAC>;
 			num-channels = <2>;
 			status = "disabled";
diff --git a/dts/bindings/dac/gd,gd32-dac.yaml b/dts/bindings/dac/gd,gd32-dac.yaml
index 251c7c62273..4210cc6db2b 100644
--- a/dts/bindings/dac/gd,gd32-dac.yaml
+++ b/dts/bindings/dac/gd,gd32-dac.yaml
@@ -14,9 +14,7 @@ properties:
     resets:
       required: true
 
-    rcu-periph-clock:
-      type: int
-      description: Reset Control Unit Peripheral Clock ID
+    clocks:
       required: true
 
     num-channels:
diff --git a/dts/riscv/gigadevice/gd32vf103.dtsi b/dts/riscv/gigadevice/gd32vf103.dtsi
index 9681122e490..b6ed6a6fbbe 100644
--- a/dts/riscv/gigadevice/gd32vf103.dtsi
+++ b/dts/riscv/gigadevice/gd32vf103.dtsi
@@ -139,7 +139,7 @@
 		dac: dac@40007400 {
 			compatible = "gd,gd32-dac";
 			reg = <0x40007400 0x400>;
-			rcu-periph-clock = <0x71d>;
+			clocks = <&cctl GD32_CLOCK_DAC>;
 			resets = <&rctl GD32_RESET_DAC>;
 			num-channels = <2>;
 			status = "disabled";