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dts: riscv: andes: rename plic-sw node to interrupt controller 

The plic-sw is the same hardware as the plic interrupt contoller and should
be used with intc_plic driver instead of separate mbox driver.

Renamed plic-sw node from "mbox: mbox-controller@e6400000" to
"plic_sw: interrupt-controller@e6400000".

Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
This commit is contained in:
Jimmy Zheng 2024-09-30 15:49:58 +08:00 committed by Carles Cufí
parent da99144891
commit 6d6c87b9fe
1 changed files with 14 additions and 6 deletions
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20
dts/riscv/andes/andes_v5_ae350.dtsi
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@ -179,12 +179,20 @@
&cpu6_intc 11 &cpu7_intc 11>;
};
mbox: mbox-controller@e6400000 {
compatible = "andestech,plic-sw";
reg = <0xe6400000 0x00400000>;
#mbox-cells = <1>;
channel-max = <30>;
status = "okay";
plic_sw: interrupt-controller@e6400000 {
compatible = "sifive,plic-1.0.0", "andestech,nceplic100";
#address-cells = <1>;
#interrupt-cells = <2>;
interrupt-controller;
reg = <0xe6400000 0x04000000>;
riscv,max-priority = <255>;
riscv,ndev = <1023>;
interrupts-extended = <&cpu0_intc 3 &cpu1_intc 3
&cpu2_intc 3 &cpu3_intc 3
&cpu4_intc 3 &cpu5_intc 3
&cpu6_intc 3 &cpu7_intc 3>;
#size-cells = <0>;
};
mtimer: timer@e6000000 {