From 66414ef6e78ff6a60f2c031e684cf0055b7c4be4 Mon Sep 17 00:00:00 2001 From: Jiafei Pan Date: Wed, 17 Aug 2022 15:43:27 +0800 Subject: [PATCH] drivers: pinctrl: fix imx pinctrl 64bit compatible Make imx pinctrl driver to be aarch64 compatible. Signed-off-by: Jiafei Pan --- drivers/pinctrl/pinctrl_imx.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/pinctrl/pinctrl_imx.c b/drivers/pinctrl/pinctrl_imx.c index d4c9213217c..cec1b19e7c3 100644 --- a/drivers/pinctrl/pinctrl_imx.c +++ b/drivers/pinctrl/pinctrl_imx.c @@ -21,7 +21,7 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uint32_t pin_ctrl_flags = pins[i].pin_ctrl_flags; #if defined(CONFIG_SOC_SERIES_IMX_RT10XX) || defined(CONFIG_SOC_SERIES_IMX_RT11XX) volatile uint32_t *gpr_register = - (volatile uint32_t *)pins[i].pinmux.gpr_register; + (volatile uint32_t *)((uintptr_t)pins[i].pinmux.gpr_register); if (gpr_register) { /* Set or clear specified GPR bit for this mux */ if (pins[i].pinmux.gpr_val) { @@ -32,14 +32,15 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, } } #endif - *((volatile uint32_t *)mux_register) = IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(mux_mode) | + *((volatile uint32_t *)((uintptr_t)mux_register)) = + IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(mux_mode) | IOMUXC_SW_MUX_CTL_PAD_SION(MCUX_IMX_INPUT_ENABLE(pin_ctrl_flags)); if (input_register) { - *((volatile uint32_t *)input_register) = + *((volatile uint32_t *)((uintptr_t)input_register)) = IOMUXC_SELECT_INPUT_DAISY(input_daisy); } if (config_register) { - *((volatile uint32_t *)config_register) = + *((volatile uint32_t *)((uintptr_t)config_register)) = pin_ctrl_flags & (~(0x1 << MCUX_IMX_INPUT_ENABLE_SHIFT)); }