diff --git a/arch/arm/core/aarch32/cortex_a_r/Kconfig b/arch/arm/core/aarch32/cortex_a_r/Kconfig
index 77cdc745575..177486cd980 100644
--- a/arch/arm/core/aarch32/cortex_a_r/Kconfig
+++ b/arch/arm/core/aarch32/cortex_a_r/Kconfig
@@ -87,6 +87,13 @@ config CPU_CORTEX_R7
 	help
 	  This option signifies the use of a Cortex-R7 CPU
 
+config CPU_CORTEX_R52
+	bool
+	select CPU_AARCH32_CORTEX_R
+	select AARCH32_ARMV8_R
+	help
+	  This option signifies the use of a Cortex-R52 CPU
+
 if CPU_AARCH32_CORTEX_R
 
 config ARMV7_R
@@ -111,6 +118,19 @@ config ARMV7_R_FP
 	  This option signifies the use of an ARMv7-R processor
 	  implementation supporting the Floating-Point Extension.
 
+config AARCH32_ARMV8_R
+	bool
+	select ATOMIC_OPERATIONS_BUILTIN
+	help
+	  This option signifies the use of an ARMv8-R AArch32 processor
+	  implementation.
+
+	  From https://developer.arm.com/products/architecture/cpu-architecture/r-profile:
+	  The Armv8-R architecture targets at the Real-time profile. It introduces
+	  virtualization at the highest security level while retaining the
+	  Protected Memory System Architecture (PMSA) based on a Memory Protection
+	  Unit (MPU). It supports the A32 and T32 instruction sets.
+
 config ARMV7_EXCEPTION_STACK_SIZE
 	int "Undefined Instruction and Abort stack size (in bytes)"
 	default 256
diff --git a/arch/arm/core/aarch32/cpu_idle.S b/arch/arm/core/aarch32/cpu_idle.S
index 5a4addf7318..7796f1f081a 100644
--- a/arch/arm/core/aarch32/cpu_idle.S
+++ b/arch/arm/core/aarch32/cpu_idle.S
@@ -134,6 +134,7 @@ SECTION_FUNC(TEXT, arch_cpu_atomic_idle)
 
 #if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE) \
 	|| defined(CONFIG_ARMV7_R) \
+	|| defined(CONFIG_AARCH32_ARMV8_R) \
 	|| defined(CONFIG_ARMV7_A)
 	/* No BASEPRI, call wfe directly
 	 * (SEVONPEND is set in z_arm_cpu_idle_init())
diff --git a/arch/arm/core/aarch32/irq_manage.c b/arch/arm/core/aarch32/irq_manage.c
index f7108c4c3ee..828a7718ac8 100644
--- a/arch/arm/core/aarch32/irq_manage.c
+++ b/arch/arm/core/aarch32/irq_manage.c
@@ -160,6 +160,7 @@ void _arch_isr_direct_pm(void)
 {
 #if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE) \
 	|| defined(CONFIG_ARMV7_R) \
+	|| defined(CONFIG_AARCH32_ARMV8_R) \
 	|| defined(CONFIG_ARMV7_A)
 	unsigned int key;
 
@@ -182,6 +183,7 @@ void _arch_isr_direct_pm(void)
 
 #if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE) \
 	|| defined(CONFIG_ARMV7_R) \
+	|| defined(CONFIG_AARCH32_ARMV8_R) \
 	|| defined(CONFIG_ARMV7_A)
 	irq_unlock(key);
 #elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
diff --git a/arch/arm/core/aarch32/isr_wrapper.S b/arch/arm/core/aarch32/isr_wrapper.S
index 5629902c39c..89012709915 100644
--- a/arch/arm/core/aarch32/isr_wrapper.S
+++ b/arch/arm/core/aarch32/isr_wrapper.S
@@ -163,7 +163,8 @@ _idle_state_cleared:
 		/* clear kernel idle state */
 		strne	r1, [r2, #_kernel_offset_to_idle]
 		blne	z_pm_save_idle_exit
-#elif defined(CONFIG_ARMV7_R) || defined(CONFIG_ARMV7_A)
+#elif defined(CONFIG_ARMV7_R) || defined(CONFIG_AARCH32_ARMV8_R) \
+	|| defined(CONFIG_ARMV7_A)
 	beq _idle_state_cleared
 	movs r1, #0
 	/* clear kernel idle state */
@@ -252,7 +253,8 @@ spurious_continue:
 	mov lr, r3
 #elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
 	pop {r0, lr}
-#elif defined(CONFIG_ARMV7_R) || defined(CONFIG_ARMV7_A)
+#elif defined(CONFIG_ARMV7_R) || defined(CONFIG_AARCH32_ARMV8_R) \
+	|| defined(CONFIG_ARMV7_A)
 	/*
 	 * r0 and lr_irq were saved on the process stack since a swap could
 	 * happen.  exc_exit will handle getting those values back
diff --git a/arch/arm/core/aarch32/swap_helper.S b/arch/arm/core/aarch32/swap_helper.S
index 70b1706f243..90452186e46 100644
--- a/arch/arm/core/aarch32/swap_helper.S
+++ b/arch/arm/core/aarch32/swap_helper.S
@@ -120,7 +120,8 @@ out_fp_endif:
      * regardless of whether the thread has an active FP context.
      */
 #endif /* CONFIG_FPU_SHARING */
-#elif defined(CONFIG_ARMV7_R) || defined(CONFIG_ARMV7_A)
+#elif defined(CONFIG_ARMV7_R) || defined(CONFIG_AARCH32_ARMV8_R) \
+	|| defined(CONFIG_ARMV7_A)
     /* Store rest of process context */
     cps #MODE_SYS
     stm r0, {r4-r11, sp}
@@ -136,7 +137,8 @@ out_fp_endif:
     movs.n r0, #_EXC_IRQ_DEFAULT_PRIO
     msr BASEPRI_MAX, r0
     isb /* Make the effect of disabling interrupts be realized immediately */
-#elif defined(CONFIG_ARMV7_R) || defined(CONFIG_ARMV7_A)
+#elif defined(CONFIG_ARMV7_R) || defined(CONFIG_AARCH32_ARMV8_R) \
+	|| defined(CONFIG_ARMV7_A)
     /*
      * Interrupts are still disabled from arch_swap so empty clause
      * here to avoid the preprocessor error below
@@ -344,7 +346,8 @@ in_fp_endif:
     /* load callee-saved + psp from thread */
     add r0, r2, #_thread_offset_to_callee_saved
     ldmia r0, {v1-v8, ip}
-#elif defined(CONFIG_ARMV7_R) || defined(CONFIG_ARMV7_A)
+#elif defined(CONFIG_ARMV7_R) || defined(CONFIG_AARCH32_ARMV8_R) \
+	|| defined(CONFIG_ARMV7_A)
 _thread_irq_disabled:
     /* load _kernel into r1 and current k_thread into r2 */
     ldr r1, =_kernel
@@ -602,7 +605,8 @@ valid_syscall_id:
     bx lr
 #endif /* CONFIG_USERSPACE */
 
-#elif defined(CONFIG_ARMV7_R) || defined(CONFIG_ARMV7_A)
+#elif defined(CONFIG_ARMV7_R) || defined(CONFIG_AARCH32_ARMV8_R) \
+	|| defined(CONFIG_ARMV7_A)
 
 /**
  *
diff --git a/arch/arm/core/aarch32/thread.c b/arch/arm/core/aarch32/thread.c
index 87689aa7bb1..41b33ac2538 100644
--- a/arch/arm/core/aarch32/thread.c
+++ b/arch/arm/core/aarch32/thread.c
@@ -563,6 +563,7 @@ void arch_switch_to_main_thread(struct k_thread *main_thread, char *stack_ptr,
 	"movs r1, #0\n\t"
 #if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE) \
 	|| defined(CONFIG_ARMV7_R) \
+	|| defined(CONFIG_AARCH32_ARMV8_R) \
 	|| defined(CONFIG_ARMV7_A)
 	"cpsie i\n\t"		/* __enable_irq() */
 #elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
diff --git a/cmake/gcc-m-cpu.cmake b/cmake/gcc-m-cpu.cmake
index 45a235191c9..efef747bb30 100644
--- a/cmake/gcc-m-cpu.cmake
+++ b/cmake/gcc-m-cpu.cmake
@@ -40,6 +40,8 @@ if("${ARCH}" STREQUAL "arm")
     set(GCC_M_CPU cortex-r5)
   elseif(CONFIG_CPU_CORTEX_R7)
     set(GCC_M_CPU cortex-r7)
+  elseif(CONFIG_CPU_CORTEX_R52)
+    set(GCC_M_CPU cortex-r52)
   elseif(CONFIG_CPU_CORTEX_A9)
     set(GCC_M_CPU cortex-a9)
   else()
diff --git a/dts/bindings/cpu/arm,cortex-r52.yaml b/dts/bindings/cpu/arm,cortex-r52.yaml
new file mode 100644
index 00000000000..3c7ca1ef5a3
--- /dev/null
+++ b/dts/bindings/cpu/arm,cortex-r52.yaml
@@ -0,0 +1,8 @@
+# Copyright (c) 2021 Arm Limited (or its affiliates). All rights reserved.
+# SPDX-License-Identifier: Apache-2.0
+
+description: This is a representation of ARM Cortex-R52 CPU.
+
+compatible: "arm,cortex-r52"
+
+include: cpu.yaml
diff --git a/include/arch/arm/aarch32/asm_inline_gcc.h b/include/arch/arm/aarch32/asm_inline_gcc.h
index 8fdce9ed632..b7af038b71a 100644
--- a/include/arch/arm/aarch32/asm_inline_gcc.h
+++ b/include/arch/arm/aarch32/asm_inline_gcc.h
@@ -61,7 +61,8 @@ static ALWAYS_INLINE unsigned int arch_irq_lock(void)
 		: "=r"(key), "=r"(tmp)
 		: "i"(_EXC_IRQ_DEFAULT_PRIO)
 		: "memory");
-#elif defined(CONFIG_ARMV7_R) || defined(CONFIG_ARMV7_A)
+#elif defined(CONFIG_ARMV7_R) || defined(CONFIG_AARCH32_ARMV8_R) \
+	|| defined(CONFIG_ARMV7_A)
 	__asm__ volatile(
 		"mrs %0, cpsr;"
 		"and %0, #" TOSTR(I_BIT) ";"
@@ -96,7 +97,8 @@ static ALWAYS_INLINE void arch_irq_unlock(unsigned int key)
 		"msr BASEPRI, %0;"
 		"isb;"
 		:  : "r"(key) : "memory");
-#elif defined(CONFIG_ARMV7_R) || defined(CONFIG_ARMV7_A)
+#elif defined(CONFIG_ARMV7_R) || defined(CONFIG_AARCH32_ARMV8_R) \
+	|| defined(CONFIG_ARMV7_A)
 	if (key != 0U) {
 		return;
 	}
diff --git a/include/arch/arm/aarch32/cortex_a_r/cmsis.h b/include/arch/arm/aarch32/cortex_a_r/cmsis.h
index 69609ca8548..95c12e0c5e3 100644
--- a/include/arch/arm/aarch32/cortex_a_r/cmsis.h
+++ b/include/arch/arm/aarch32/cortex_a_r/cmsis.h
@@ -46,6 +46,8 @@ extern "C" {
 #include <core_cr5.h>
 #elif defined(CONFIG_CPU_CORTEX_R7)
 #include <core_cr7.h>
+#elif defined(CONFIG_CPU_CORTEX_R52)
+#include <core_cr52.h>
 #elif defined(CONFIG_CPU_AARCH32_CORTEX_A)
 /*
  * Any defines relevant for the proper inclusion of CMSIS' Cortex-A
diff --git a/include/arch/arm/aarch32/error.h b/include/arch/arm/aarch32/error.h
index 975da29b48c..e54dd7d1c5a 100644
--- a/include/arch/arm/aarch32/error.h
+++ b/include/arch/arm/aarch32/error.h
@@ -53,7 +53,8 @@ do { \
 		: [reason] "i" (reason_p), [id] "i" (_SVC_CALL_RUNTIME_EXCEPT) \
 		: "memory"); \
 } while (false)
-#elif defined(CONFIG_ARMV7_R) || defined(CONFIG_ARMV7_A)
+#elif defined(CONFIG_ARMV7_R) || defined(CONFIG_AARCH32_ARMV8_R) \
+	|| defined(CONFIG_ARMV7_A)
 /*
  * In order to support using svc for an exception while running in an
  * isr, stack $lr_svc before calling svc.  While exiting the isr,