doc: boards: align main board image name with board name

As per board porting guidelines, the board image should be named after
the board.
This commit implements the changes for boards found to be non-compliant.

Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>

boards/actinius/icarus_som_dk/doc/index.rst

@@ -6,7 +6,7 @@ Actinius Icarus SoM DK
 Overview
 ********
 
-.. figure:: img/icarus-som-dk.jpg
+.. figure:: img/icarus_som_dk.jpg
      :width: 450px
      :align: center
      :alt: Icarus SoM DK
@@ -42,7 +42,7 @@ following devices (provided directly by Nordic):
 * :abbr:`WDT (Watchdog Timer)`
 * :abbr:`IDAU (Implementation Defined Attribution Unit)`
 
-.. figure:: img/icarus-som-dk-block-diagram.jpg
+.. figure:: img/icarus_som_dk_block_diagram.jpg
      :width: 450px
      :align: center
      :alt: Icarus SoM DK Block Diagram

boards/efinix/titanium_ti60_f225/doc/index.rst

@@ -11,7 +11,7 @@ high performance with the lowest possible power on a small physical size. In add
 which is a user-configurable RISC-V SoC based on the VexRiscv core with configurable feature set and extension.
 Using the Efinity IP Manager, you can configure the SoC to include only the peripherals that you require.
 
-.. figure:: img/ti60f225-board-top.jpg
+.. figure:: img/titanium_ti60_f225.jpg
    :align: center
    :alt: titanium_ti60_f225_board
 

boards/espressif/esp32_ethernet_kit/doc/index.rst

@@ -13,7 +13,7 @@ over Ethernet (PoE).
 
 .. _get-started-esp32-ethernet-kit-v1.2-overview:
 
-.. figure:: img/esp32-ethernet-kit-v1.2-overview.jpg
+.. figure:: img/esp32_ethernet_kit.jpg
     :align: center
     :alt: ESP32-Ethernet-Kit V1.2
     :figclass: align-center

boards/espressif/esp_wrover_kit/doc/index.rst

@@ -43,7 +43,7 @@ Functional Description
 The following two figures and the table below describe the key components, interfaces, and controls
 of the ESP-WROVER-KIT board.
 
-.. figure:: img/esp-wrover-kit-v4.1-layout-front.jpg
+.. figure:: img/esp_wrover_kit.jpg
      :align: center
      :alt: esp wrover front
 

boards/intel/socfpga_std/cyclonev_socdk/doc/index.rst

@@ -10,7 +10,7 @@ Overview
 The Zephyr kernel is supported on the Intel® Cyclone® V SoC Development Kit,
 using its Hard Processor System (HPS) CPU.
 
-.. figure:: img/cv_soc_board.jpg
+.. figure:: img/cyclonev_socdk.jpg
    :align: center
    :alt: Intel's Cyclone® V SoC FPGA DevKit
 

boards/renesas/ek_ra4m2/doc/index.rst

@@ -61,7 +61,7 @@ available internal to the RA MCU
 **Special Feature Access**
 - 32 MB (256 Mb) External Quad-SPI Flash
 
-.. figure:: ek-ra4m2-board.webp
+.. figure:: ek_ra4m2.webp
 	:align: center
 	:alt: RA4M2 Evaluation Kit
 

boards/renesas/ek_ra6m3/doc/index.rst

@@ -59,7 +59,7 @@ The key features of the EK-RA6M3 board are categorized in three groups as follow
 - USB High Speed Host and Device (micro-AB connector)
 - 32 Mb (256 Mb) External Quad-SPI Flash
 
-.. figure:: ek-ra6m3-board.webp
+.. figure:: ek_ra6m3.webp
 	:align: center
 	:alt: RA6M3 Evaluation Kit
 

boards/renesas/ek_ra8m1/doc/index.rst

@@ -61,7 +61,7 @@ The key features of the EK-RA8M1 board are categorized in three groups as follow
 - 512 Mb (64 MB) External Octo-SPI Flash (present in the MCU Native Pin Access area of the EK-RA8M1 board)
 - CAN FD (3-pin header)
 
-.. figure:: ek-ra8m1-board.jpg
+.. figure:: ek_ra8m1.jpg
 	:align: center
 	:alt: RA8M1 Evaluation Kit
 

boards/renesas/fpb_ra6e1/doc/index.rst

@@ -46,7 +46,7 @@ The key features of the FPB-RA6E1 board are categorized in three groups as follo
 
 - MCU boot configuration jumper
 
-.. figure:: fpb-ra6e1-board.webp
+.. figure:: fpb_ra6e1.webp
 	:align: center
 	:alt: RA6E1 Evaluation Kit