From 4de10f353e611ff3c02dbc15ca9c031ef81aabca Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Benjamin=20Cab=C3=A9?= Date: Fri, 18 Oct 2024 15:40:54 +0200 Subject: [PATCH] boards: efinix: adopt new zephyr:board directive and role MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This updates the documentation of all the Efinix boards to use the new `zephyr:board::` directive. Signed-off-by: Benjamin Cabé --- boards/efinix/titanium_ti60_f225/doc/index.rst | 11 +---------- 1 file changed, 1 insertion(+), 10 deletions(-) diff --git a/boards/efinix/titanium_ti60_f225/doc/index.rst b/boards/efinix/titanium_ti60_f225/doc/index.rst index 40338736308..ec193126434 100644 --- a/boards/efinix/titanium_ti60_f225/doc/index.rst +++ b/boards/efinix/titanium_ti60_f225/doc/index.rst @@ -1,7 +1,4 @@ -.. _titanium_ti60_f225: - -Efinix Titanium Ti60 F225 -######################### +.. zephyr:board:: titanium_ti60_f225 Overview ******** @@ -11,12 +8,6 @@ high performance with the lowest possible power on a small physical size. In add which is a user-configurable RISC-V SoC based on the VexRiscv core with configurable feature set and extension. Using the Efinity IP Manager, you can configure the SoC to include only the peripherals that you require. -.. figure:: img/titanium_ti60_f225.jpg - :align: center - :alt: titanium_ti60_f225_board - -Figure is the development board - Board block diagram *******************