diff --git a/boards/ene/index.rst b/boards/ene/index.rst new file mode 100644 index 00000000000..aea3d8ee661 --- /dev/null +++ b/boards/ene/index.rst @@ -0,0 +1,10 @@ +.. _boards-ene: + +ENE +### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/ene/kb1200_evb/Kconfig.kb1200_evb b/boards/ene/kb1200_evb/Kconfig.kb1200_evb new file mode 100644 index 00000000000..6cf67b86769 --- /dev/null +++ b/boards/ene/kb1200_evb/Kconfig.kb1200_evb @@ -0,0 +1,5 @@ +# Copyright (c) 2023 ENE Technology Inc. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_KB1200_EVB + select SOC_KB1200 diff --git a/boards/ene/kb1200_evb/board.cmake b/boards/ene/kb1200_evb/board.cmake new file mode 100644 index 00000000000..cab2daca270 --- /dev/null +++ b/boards/ene/kb1200_evb/board.cmake @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(jlink "--device=KB1200" "--speed=4000") + +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/ene/kb1200_evb/board.yml b/boards/ene/kb1200_evb/board.yml new file mode 100644 index 00000000000..d8dd4b412c7 --- /dev/null +++ b/boards/ene/kb1200_evb/board.yml @@ -0,0 +1,5 @@ +board: + name: kb1200_evb + vendor: ene + socs: + - name: kb1200 diff --git a/boards/ene/kb1200_evb/doc/index.rst b/boards/ene/kb1200_evb/doc/index.rst new file mode 100644 index 00000000000..6558b8dad54 --- /dev/null +++ b/boards/ene/kb1200_evb/doc/index.rst @@ -0,0 +1,86 @@ +.. _ene_kb1200_evb: + +ENE KB1200_EVB +############## + +Overview +******** + +The KB1200_EVB kit is a development platform to evaluate the +ENE KB1200 series microcontrollers. This board needs to be mated with +part number KB1200. + + +Hardware +******** + +- ARM Cortex-M4F Processor +- 512KB Flash and 320KB RAM +- ADC & GPIO headers +- SER1, SER2 and SER3 +- FAN PWM interface +- ENE Debug interface + +Supported Features +================== + +The following features are supported: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| ADC | on-chip | adc controller | ++-----------+------------+-------------------------------------+ +| CLOCK | on-chip | reset and clock control | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c port/controller | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| PMU | on-chip | power management | ++-----------+------------+-------------------------------------+ +| PSL | on-chip | power switch logic | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pulse width modulator | ++-----------+------------+-------------------------------------+ +| TACH | on-chip | tachometer sensor | ++-----------+------------+-------------------------------------+ +| SER | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+-------------------------------------+ + +Other hardware features are not currently supported by Zephyr (at the moment) + +System Clock +============ + +The KB1200 MCU is configured to use the 96Mhz internal oscillator with the +on-chip DPLL to generate a resulting EC clock rate of 96MHz/48MHz/24MHz/12MHz. +See Processor clock control register (refer 5.1 General Configuration) + +Programming and Debugging +************************* + +Flashing +======== + +If the correct headers are installed, this board supports SWD Debug Interface. + +To flash with SWD, install the drivers for your programmer, for example: +SEGGER J-link's drivers are at https://www.segger.com/downloads/jlink/ + +Debugging +========= + +Use SWD with a J-Link + +References +========== + +.. target-notes:: diff --git a/boards/ene/kb1200_evb/kb1200_evb.dts b/boards/ene/kb1200_evb/kb1200_evb.dts new file mode 100644 index 00000000000..b6baf1a55d1 --- /dev/null +++ b/boards/ene/kb1200_evb/kb1200_evb.dts @@ -0,0 +1,157 @@ +/* + * Copyright (c) 2023 ENE Technology Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include +#include +#include + +/ { + model = "KB1200 board"; + compatible = "ene,kb1200"; + + aliases { + uart0 = &uart0; + led0 = &led0; + led1 = &led1; + sw0 = &user_button; + }; + + chosen { + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + }; + + gpio_keys { + compatible = "gpio-keys"; + user_button: button { + label = "User"; + gpios = <&gpio0x1x 0x10 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + zephyr,code = ; + }; + }; + + leds { + compatible = "gpio-leds"; + /* green led */ + led0: led_0 { + gpios = <&gpio0x1x 0x0f GPIO_ACTIVE_HIGH>; + label = "LED0"; + }; + /* blue led */ + led1: led_1 { + gpios = <&gpio0x1x 0x11 GPIO_ACTIVE_HIGH>; + label = "LED1"; + }; + }; +}; + +&uart0 { + pinctrl-0 = <&uart0_tx_gpio03 &uart0_rx_gpio01>; + pinctrl-names = "default"; + status = "okay"; + current-speed = <115200>; +}; + +&uart1 { + pinctrl-0 = <&uart1_tx_gpio36 &uart1_rx_gpio28>; + pinctrl-names = "default"; + status = "okay"; + current-speed = <115200>; +}; + +&uart2 { + pinctrl-0 = <&uart2_tx_gpio04 &uart2_rx_gpio55>; + pinctrl-names = "default"; + status = "okay"; + current-speed = <115200>; +}; + +&gpio0x1x { + status = "okay"; +}; + +&adc0 { + status = "okay"; + pinctrl-0 = <&adc0_gpio0a &adc1_gpio0b &adc2_gpio0c &adc3_gpio0d>; + pinctrl-names = "default"; +}; + +&pwm0 { + status = "okay"; + pinctrl-0 = <&pwm0_gpio3a>; + pinctrl-names = "default"; +}; + +&pwm4 { + status = "okay"; + pinctrl-0 = <&pwm4_gpio31>; + pinctrl-names = "default"; +}; + +&pwm5 { + status = "okay"; + pinctrl-0 = <&pwm5_gpio30>; + pinctrl-names = "default"; +}; + +&pwm6 { + status = "okay"; + pinctrl-0 = <&pwm6_gpio37>; + pinctrl-names = "default"; +}; + +&tach0 { + status = "okay"; + pinctrl-0 = <&tach0_gpio48>; + pinctrl-names = "default"; + pulses-per-round = <2>; + sample-time-us = <2>; +}; + +&tach1 { + status = "okay"; + pinctrl-0 = <&tach1_gpio4e>; + pinctrl-names = "default"; + pulses-per-round = <1>; + sample-time-us = <8>; +}; + +&tach2 { + status = "okay"; + pinctrl-0 = <&tach2_gpio0e>; + pinctrl-names = "default"; + pulses-per-round = <2>; + sample-time-us = <16>; +}; + +&tach3 { + status = "okay"; + pinctrl-0 = <&tach3_gpio43>; + pinctrl-names = "default"; + pulses-per-round = <1>; + sample-time-us = <64>; +}; + +&wdt0 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + clock-frequency = ; + pinctrl-0 = <&i2c0_clk_gpio2c &i2c0_dat_gpio2d>; + pinctrl-names = "default"; +}; + +&i2c8 { + status = "okay"; + clock-frequency = ; + pinctrl-0 = <&i2c8_clk_gpio70 &i2c8_dat_gpio71>; + pinctrl-names = "default"; +}; diff --git a/boards/ene/kb1200_evb/kb1200_evb.yaml b/boards/ene/kb1200_evb/kb1200_evb.yaml new file mode 100644 index 00000000000..efa85b9c830 --- /dev/null +++ b/boards/ene/kb1200_evb/kb1200_evb.yaml @@ -0,0 +1,13 @@ +identifier: kb1200_evb +name: KB1200 EVB +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - gpio + - uart +ram: 64 +flash: 256 diff --git a/boards/ene/kb1200_evb/kb1200_evb_defconfig b/boards/ene/kb1200_evb/kb1200_evb_defconfig new file mode 100644 index 00000000000..5dfbb78fbf7 --- /dev/null +++ b/boards/ene/kb1200_evb/kb1200_evb_defconfig @@ -0,0 +1,11 @@ +# Copyright (c) 2023 ENE Technology Inc. +# SPDX-License-Identifier: Apache-2.0 + +# Enable console & UART driver +CONFIG_SERIAL=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_UART_INTERRUPT_DRIVEN=y + +# Enable GPIO +CONFIG_GPIO=y diff --git a/boards/ene/kb1200_evb/support/openocd.cfg b/boards/ene/kb1200_evb/support/openocd.cfg new file mode 100644 index 00000000000..56444e04413 --- /dev/null +++ b/boards/ene/kb1200_evb/support/openocd.cfg @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +source [find interface/jlink.cfg] + +transport select swd + +source [find target/swj-dp.tcl] + + +# Set Chipname +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME kb1200 +} + +# SWD DAP ID of ENE KB1200 Cortex-M4. +if { [info exists CPUDAPID ] } { + set _CPUDAPID $CPUDAPID +} else { + set _CPUDAPID 0x2ba01477 +} + +# Work-area is a space in RAM used for flash programming +# By default use 32kB +if { [info exists WORKAREASIZE] } { + set _WORKAREASIZE $WORKAREASIZE +} else { + set _WORKAREASIZE 0x8000 +} + +# Debug Adapter Target Settings +swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUDAPID +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME cortex_m -endian little -dap $_CHIPNAME.dap + +$_TARGETNAME configure -work-area-phys 0x200c0000 -work-area-size $_WORKAREASIZE -work-area-backup 0 + +# Initial JTAG/SWD speed +# For safety purposes, set for the lowest cpu clock configuration +# 4MHz / 6 = 666KHz, so use 600KHz for it +adapter speed 600 + +# For safety purposes, set for the lowest cpu clock configuration +$_TARGETNAME configure -event reset-start {adapter speed 600} + +# use sysresetreq to perform a system reset +cortex_m reset_config sysresetreq + +# ENE internal spi flash +flash bank ispif eneispif 0x60000000 0 0 0 $_TARGETNAME 0x50101000