soc: nordic: Disable asserts on ppr and flpr
Asserts are by default enabled for tests but flpr and ppr are small cores (<64k) and many tests does not fit in memory with asserts enabled. Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
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@ -6,4 +6,8 @@ if SOC_NRF54H20_CPUFLPR
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config NUM_IRQS
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config NUM_IRQS
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default 496
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default 496
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# As FLPR has limited memory most of tests does not fit with asserts enabled.
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config ASSERT
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default n
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endif # SOC_NRF54H20_CPUFLPR
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endif # SOC_NRF54H20_CPUFLPR
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@ -8,5 +8,9 @@ config NUM_IRQS
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config SYS_CLOCK_TICKS_PER_SEC
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config SYS_CLOCK_TICKS_PER_SEC
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default 1000
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default 1000
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#
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# As PPR has limited memory most of tests does not fit with asserts enabled.
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config ASSERT
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default n
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endif # SOC_NRF54H20_CPUPPR
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endif # SOC_NRF54H20_CPUPPR
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@ -8,4 +8,8 @@ if SOC_NRF54L15_CPUFLPR
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config NUM_IRQS
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config NUM_IRQS
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default 287
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default 287
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# As FLPR has limited memory most of tests does not fit with asserts enabled.
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config ASSERT
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default n
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endif # SOC_NRF54L15_CPUFLPR
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endif # SOC_NRF54L15_CPUFLPR
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@ -11,5 +11,8 @@ config RISCV_HAS_CPU_IDLE
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config NUM_IRQS
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config NUM_IRQS
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int
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int
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default 287
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default 287
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# As FLPR has limited memory most of tests does not fit with asserts enabled.
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config ASSERT
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default n
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endif # SOC_NRF54L15_ENGA_CPUFLPR
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endif # SOC_NRF54L15_ENGA_CPUFLPR
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@ -12,4 +12,8 @@ config SYS_CLOCK_TICKS_PER_SEC
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config RV_BOOT_HART
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config RV_BOOT_HART
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default 13 if SOC_NRF9230_ENGB
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default 13 if SOC_NRF9230_ENGB
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# As FLPR has limited memory most of tests does not fit with asserts enabled.
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config ASSERT
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default n
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endif # SOC_NRF9280_CPUPPR
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endif # SOC_NRF9280_CPUPPR
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