From 0fa766c8ea1cee33167be1bce87995e12cb4b774 Mon Sep 17 00:00:00 2001
From: Neil Chen <cheng.chen_1@nxp.com>
Date: Sat, 12 Oct 2024 15:52:31 +0800
Subject: [PATCH] tests: drivers/regulator/voltage: Add regulator test for NXP
 frdm_mcxn236

Support regulator(vref) output vt oltage test for NXP frdm_mcxn236

Signed-off-by: Neil Chen <cheng.chen_1@nxp.com>
---
 .../voltage/boards/frdm_mcxn236.overlay       | 47 +++++++++++++++++++
 1 file changed, 47 insertions(+)
 create mode 100644 tests/drivers/regulator/voltage/boards/frdm_mcxn236.overlay

diff --git a/tests/drivers/regulator/voltage/boards/frdm_mcxn236.overlay b/tests/drivers/regulator/voltage/boards/frdm_mcxn236.overlay
new file mode 100644
index 00000000000..93fa4cf184e
--- /dev/null
+++ b/tests/drivers/regulator/voltage/boards/frdm_mcxn236.overlay
@@ -0,0 +1,47 @@
+/*
+ * Copyright 2024 NXP
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/adc/adc.h>
+#include <zephyr/dt-bindings/adc/mcux-lpadc.h>
+#include <zephyr/dt-bindings/regulator/nxp_vref.h>
+
+/* To do this test, connect LPADC0 channel 2A(J8 pin 12) to VREF_OUT (J2 pin 19) */
+
+/ {
+	resources: resources {
+		compatible = "test-regulator-voltage";
+		regulators = <&vref>;
+		tolerance-microvolt = <10000>;
+		set-read-delay-ms = <1>;
+		adc-avg-count = <10>;
+		io-channels = <&lpadc0 0>;
+		min-microvolt = <1000000>;
+		max-microvolt = <2100000>;
+	};
+};
+
+&vref {
+	regulator-initial-mode = <NXP_VREF_MODE_INTERNAL_REGULATOR>;
+};
+
+&lpadc0 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	/* In this case, the LPADC reference source cannot be set to VREFO,
+	 * switch the reference source to VDD_ANA.
+	 */
+	voltage-ref= <2>;
+
+	channel@0 {
+		reg = <0>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_EXTERNAL0";
+		zephyr,vref-mv = <3300>;
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,resolution = <12>;
+		zephyr,input-positive = <MCUX_LPADC_CH2A>;
+	};
+};