soc/sifive/sifive-freedom: enable PMP by default on 64-bit SoCs
This commit enables PMP on 64-bit SoCs from the SiFive Freedom SoC series by default. This change is needed to e.g. run the Userspace Hello World demo. Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
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@ -5,17 +5,21 @@
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config SOC_SERIES_SIFIVE_FREEDOM_FU500
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config SOC_SERIES_SIFIVE_FREEDOM_FU500
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bool
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bool
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select 64BIT
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# RISC-V options
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# RISC-V options
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select RISCV
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select RISCV
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select RISCV_PRIVILEGED
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select RISCV_PRIVILEGED
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select RISCV_HAS_PLIC
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select RISCV_HAS_PLIC
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select RISCV_PMP
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select RISCV_ISA_RV64I
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select RISCV_ISA_RV64I
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select RISCV_ISA_EXT_M
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select RISCV_ISA_EXT_M
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select RISCV_ISA_EXT_A
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select RISCV_ISA_EXT_A
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select RISCV_ISA_EXT_C
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select RISCV_ISA_EXT_C
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select RISCV_ISA_EXT_ZICSR
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select RISCV_ISA_EXT_ZICSR
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select RISCV_ISA_EXT_ZIFENCEI
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select RISCV_ISA_EXT_ZIFENCEI
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imply XIP
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select SOC_EARLY_INIT_HOOK
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select SOC_EARLY_INIT_HOOK
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select 64BIT
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select INCLUDE_RESET_VECTOR
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select INCLUDE_RESET_VECTOR
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imply XIP
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@ -4,17 +4,21 @@
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config SOC_SERIES_SIFIVE_FREEDOM_FU700
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config SOC_SERIES_SIFIVE_FREEDOM_FU700
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bool
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bool
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select 64BIT
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# RISC-V options
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# RISC-V options
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select RISCV
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select RISCV
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select RISCV_PRIVILEGED
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select RISCV_PRIVILEGED
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select RISCV_HAS_PLIC
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select RISCV_HAS_PLIC
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select RISCV_PMP
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select RISCV_ISA_RV64I
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select RISCV_ISA_RV64I
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select RISCV_ISA_EXT_M
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select RISCV_ISA_EXT_M
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select RISCV_ISA_EXT_A
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select RISCV_ISA_EXT_A
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select RISCV_ISA_EXT_C
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select RISCV_ISA_EXT_C
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select RISCV_ISA_EXT_ZICSR
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select RISCV_ISA_EXT_ZICSR
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select RISCV_ISA_EXT_ZIFENCEI
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select RISCV_ISA_EXT_ZIFENCEI
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imply XIP
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select SOC_EARLY_INIT_HOOK
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select SOC_EARLY_INIT_HOOK
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select INCLUDE_RESET_VECTOR
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select INCLUDE_RESET_VECTOR
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select 64BIT
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imply XIP
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