From 07877446846f51250a17f313367786ff7c4c63af Mon Sep 17 00:00:00 2001
From: Yong Cong Sin <ycsin@meta.com>
Date: Wed, 7 Aug 2024 20:13:48 +0800
Subject: [PATCH] tests: arch: common: stack_unwind: add qemu_riscv32e

qemu_riscv32e uses a different ISA and is kinda special, add it
to the testcase for better coverage.

Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
---
 tests/arch/common/stack_unwind/testcase.yaml | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/tests/arch/common/stack_unwind/testcase.yaml b/tests/arch/common/stack_unwind/testcase.yaml
index a142137bfbd..a6d6c52c30a 100644
--- a/tests/arch/common/stack_unwind/testcase.yaml
+++ b/tests/arch/common/stack_unwind/testcase.yaml
@@ -7,6 +7,7 @@ tests:
   arch.common.stack_unwind.riscv_fp:
     arch_allow: riscv
     integration_platforms:
+      - qemu_riscv32e
       - qemu_riscv32
       - qemu_riscv64
     extra_configs:
@@ -20,6 +21,7 @@ tests:
   arch.common.stack_unwind.riscv_sp:
     arch_allow: riscv
     integration_platforms:
+      - qemu_riscv32e
       - qemu_riscv32
       - qemu_riscv64
     harness_config:
@@ -58,6 +60,7 @@ tests:
       - riscv
       - arm64
     integration_platforms:
+      - qemu_riscv32e
       - qemu_riscv32
       - qemu_riscv64
       - qemu_cortex_a53