110 lines
2.0 KiB
Plaintext
110 lines
2.0 KiB
Plaintext
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# Kconfig - ADC configuration options
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#
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# Copyright (c) 2015 Intel Corporation
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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menuconfig ADC_DW
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bool "ARC Designware Driver"
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depends on ARC
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select ADC_0
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default n
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help
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Enable the driver implementation of the Designware ADC IP.
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if ADC_DW
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config ADC_DW_CALIBRATION
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bool "Enable Calibration"
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default y
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help
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Enables ADC to run with a calibrated output at the
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expense of execution speed when exiting low power states.
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If disabled, the ADC will require the application/system-integrator
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to provide a calibration method.
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config ADC_DW_DUMMY_CONVERSION
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bool "Enable dummy conversion"
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default y
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help
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After awaking from low power state a dummy
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conversion must be performed and discarded.
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If disabled the user will have to discard the first
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sample after a resume from a low power state.
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choice
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prompt "Output Mode"
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default ADC_DW_SERIAL
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help
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ADC output mode: parallel or serial.
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config ADC_DW_SERIAL
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bool "Serial"
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config ADC_DW_PARALLEL
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bool "Parallel"
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endchoice
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choice
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prompt "Sequence Mode"
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default ADC_DW_SINGLESHOT
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help
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ADC sequence mode - single run/repetitive
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config ADC_DW_SINGLESHOT
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bool "Single Ended"
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config ADC_DW_REPETITIVE
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bool "Differential"
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endchoice
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choice
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prompt "Capture Mode"
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default ADC_DW_RISING_EDGE
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help
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ADC controller capture mode:
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by rising or falling edge of adc_clk
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config ADC_DW_RISING_EDGE
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bool "Rising Edge"
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config ADC_DW_FALLING_EDGE
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bool "Falling Edge"
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endchoice
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config ADC_DW_SAMPLE_WIDTH
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int "Sample Width"
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default 31
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help
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Defines ADC device data sample width (resolution):
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- 0 = 6 bits resolution
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- 1 = 8 bits resolution
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- 2 = 10 bits resolution
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- 3 = 12 bits resolution
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config ADC_DW_SERIAL_DELAY
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int "Serial Delay"
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default 1
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help
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Number of ADC clock ticks that the first bit of
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the serial output is delayed after the conversion
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has started.
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config ADC_DW_CLOCK_RATIO
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int "Clock Ratio"
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default 1024
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help
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ADC Clock Ratio
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endif # ADC_DW
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