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zephyr/boards/arm/pinnacle_100_dvk/pinnacle_100_dvk_defconfig

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boards: arm: pinnacle_100_dvk: Update clock error The 32KHz crystal used is a tuning fork crystal which can have a larger clock drift over temperature than an AT cut crystal, therefore the LFXO clock source error rate needs updating to account for this possible drift over temperature. Signed-off-by: Jamie McCrae <jamie.mccrae@lairdconnect.com>
2021-08-06 16:49:48 +08:00
# Copyright (c) 2020-2021 Laird Connectivity
boards: add Pinnacle 100 DVK Add Laird Connectivity Pinnacle 100 modem. Signed-off-by: Ryan Erickson <ryan.erickson@lairdconnect.com>
2020-09-09 09:19:29 +08:00
# SPDX-License-Identifier: Apache-2.0
CONFIG_SOC_SERIES_NRF52X=y
CONFIG_SOC_NRF52840_QIAA=y
CONFIG_BOARD_PINNACLE_100_DVK=y
# Enable MPU
CONFIG_ARM_MPU=y
# Enable RTT
CONFIG_USE_SEGGER_RTT=y
boards: arm: pinnacle_100_dvk: Update clock error The 32KHz crystal used is a tuning fork crystal which can have a larger clock drift over temperature than an AT cut crystal, therefore the LFXO clock source error rate needs updating to account for this possible drift over temperature. Signed-off-by: Jamie McCrae <jamie.mccrae@lairdconnect.com>
2021-08-06 16:49:48 +08:00
# Enable GPIO
boards: add Pinnacle 100 DVK Add Laird Connectivity Pinnacle 100 modem. Signed-off-by: Ryan Erickson <ryan.erickson@lairdconnect.com>
2020-09-09 09:19:29 +08:00
CONFIG_GPIO=y
boards: arm: pinnacle_100_dvk: Update clock error The 32KHz crystal used is a tuning fork crystal which can have a larger clock drift over temperature than an AT cut crystal, therefore the LFXO clock source error rate needs updating to account for this possible drift over temperature. Signed-off-by: Jamie McCrae <jamie.mccrae@lairdconnect.com>
2021-08-06 16:49:48 +08:00
# Enable uart driver
boards: add Pinnacle 100 DVK Add Laird Connectivity Pinnacle 100 modem. Signed-off-by: Ryan Erickson <ryan.erickson@lairdconnect.com>
2020-09-09 09:19:29 +08:00
CONFIG_SERIAL=y
boards: arm: pinnacle_100_dvk: Update clock error The 32KHz crystal used is a tuning fork crystal which can have a larger clock drift over temperature than an AT cut crystal, therefore the LFXO clock source error rate needs updating to account for this possible drift over temperature. Signed-off-by: Jamie McCrae <jamie.mccrae@lairdconnect.com>
2021-08-06 16:49:48 +08:00
# Enable console
boards: add Pinnacle 100 DVK Add Laird Connectivity Pinnacle 100 modem. Signed-off-by: Ryan Erickson <ryan.erickson@lairdconnect.com>
2020-09-09 09:19:29 +08:00
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
boards: arm: pinnacle_100_dvk: Update clock error The 32KHz crystal used is a tuning fork crystal which can have a larger clock drift over temperature than an AT cut crystal, therefore the LFXO clock source error rate needs updating to account for this possible drift over temperature. Signed-off-by: Jamie McCrae <jamie.mccrae@lairdconnect.com>
2021-08-06 16:49:48 +08:00
# Additional board options
boards: add Pinnacle 100 DVK Add Laird Connectivity Pinnacle 100 modem. Signed-off-by: Ryan Erickson <ryan.erickson@lairdconnect.com>
2020-09-09 09:19:29 +08:00
CONFIG_GPIO_AS_PINRESET=y
boards: arm: pinnacle_100_dvk: Update clock error The 32KHz crystal used is a tuning fork crystal which can have a larger clock drift over temperature than an AT cut crystal, therefore the LFXO clock source error rate needs updating to account for this possible drift over temperature. Signed-off-by: Jamie McCrae <jamie.mccrae@lairdconnect.com>
2021-08-06 16:49:48 +08:00
# 32KHz clock source
CONFIG_CLOCK_CONTROL_NRF_K32SRC_XTAL=y
CONFIG_CLOCK_CONTROL_NRF_K32SRC_150PPM=y
boards: arm: pinnacle_100_dvk: migrate to pinctrl Use pinctrl instead of `-pin` properties. Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-03-17 20:18:27 +08:00
CONFIG_PINCTRL=y